From patchwork Fri Jun 24 11:41:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 12894382 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D14E7C433EF for ; Fri, 24 Jun 2022 11:42:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbiFXLmQ (ORCPT ); Fri, 24 Jun 2022 07:42:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229653AbiFXLmM (ORCPT ); Fri, 24 Jun 2022 07:42:12 -0400 Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [IPv6:2001:4d48:ad52:32c8:5054:ff:fe00:142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B110F77070 for ; Fri, 24 Jun 2022 04:42:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=KWK8sKKLFR+68SMkB5FGReiHrYFC6ByuHPtr0wPhHIU=; b=arZlWD7mHWArRlT+F7dIYh8TiR csaPvCRlYX8uHAk1FyUEYkllNJpgH9peys+JQw2Q8R35yRtGJGR8ItoeJfQ3gDV9rAhZbs93NN6Du lPVd6VoMdNx84iQ16cxzxdhz/fGKi+7RpMI2rFzOXVMgJC56tXcjVkAfphym+HNynmpMurk6k82Xh b6moYKALL3UfIkFmn6btQnFoFzdhKuLHwvhrz4Y8oZuFS1YT3RC8HH79D98ySg0Shd0IxKzM2va+X 8fINmX8Qvg7EmWfNiKxh4OywEOiQvUnLoImwJ6PFxkxB13KsPRp7E/mqo6o/7UoHFbKA5wYvYp7DD AbBonOJA==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:41612 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o4hhH-0005rx-VE; Fri, 24 Jun 2022 12:41:59 +0100 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1o4hhH-004Aor-AF; Fri, 24 Jun 2022 12:41:59 +0100 In-Reply-To: References: From: "Russell King (Oracle)" To: Andrew Lunn , Heiner Kallweit Cc: Alexandre Belloni , "Alvin __ipraga" , Claudiu Manoil , "David S. Miller" , DENG Qingfang , Eric Dumazet , Florian Fainelli , George McCollister , Hauke Mehrtens , Jakub Kicinski , Kurt Kanzenbach , Landen Chao , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Matthias Brugger , netdev@vger.kernel.org, Paolo Abeni , Sean Wang , UNGLinuxDriver@microchip.com, Vivien Didelot , Vladimir Oltean , Woojung Huh Subject: [PATCH RFC net-next 2/4] net: dsa: mv88e6xxx: report the default interface mode for the port MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Fri, 24 Jun 2022 12:41:59 +0100 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Report the maximum speed interface mode for the port, or if we don't have that information, the hardware configured interface mode for the port. This allows phylink to know which interface mode CPU and DSA ports are operating, which will be necessary when we want to select the maximum speed for the port (required for such ports without a PHY or fixed-link specified in firmware.) Signed-off-by: Russell King (Oracle) --- drivers/net/dsa/mv88e6xxx/chip.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index f98be98551ef..1c6b4b00d58d 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -823,6 +823,7 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, phy_interface_t *default_interface) { struct mv88e6xxx_chip *chip = ds->priv; + u8 cmode = chip->ports[port].cmode; chip->info->ops->phylink_get_caps(chip, port, config); @@ -830,6 +831,14 @@ static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, if (mv88e6xxx_phy_is_internal(ds, port)) __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces); + + if (chip->info->ops->port_max_speed_mode) + *default_interface = chip->info->ops->port_max_speed_mode(port); + else if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && + mv88e6xxx_phy_interface_modes[cmode]) + *default_interface = mv88e6xxx_phy_interface_modes[cmode]; + else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) + *default_interface = PHY_INTERFACE_MODE_RGMII; } static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,