| Message ID | E1tffRE-003Z5c-0L@rmk-PC.armlinux.org.uk (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: xpcs: cleanups and partial support for KSZ9477 | expand |
> -----Original Message----- > From: Russell King <rmk@armlinux.org.uk> On Behalf Of Russell King (Oracle) > Sent: Wednesday, February 5, 2025 5:28 AM > To: Tristram Ha - C24268 <Tristram.Ha@microchip.com> > Cc: Vladimir Oltean <olteanv@gmail.com>; UNGLinuxDriver > <UNGLinuxDriver@microchip.com>; Woojung Huh - C21699 > <Woojung.Huh@microchip.com>; Andrew Lunn <andrew@lunn.ch>; Heiner Kallweit > <hkallweit1@gmail.com>; David S. Miller <davem@davemloft.net>; Eric Dumazet > <edumazet@google.com>; Jakub Kicinski <kuba@kernel.org>; Paolo Abeni > <pabeni@redhat.com>; netdev@vger.kernel.org > Subject: [PATCH RFC net-next 1/4] net: xpcs: add support for configuring width of > 10/100M MII connection > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content > is safe > > When in SGMII mode, the hardware can be configured to use either 4-bit > or 8-bit MII connection. Currently, we don't change this bit for most > implementations with the exception of TXGBE requiring 8-bit. Move this > decision to the creation code and act on it when configuring SGMII. > > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> > --- > drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++++++---- > drivers/net/pcs/pcs-xpcs.h | 8 ++++++++ > 2 files changed, 23 insertions(+), 4 deletions(-) > > diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c > index 1faa37f0e7b9..12a3d5a80b45 100644 > --- a/drivers/net/pcs/pcs-xpcs.c > +++ b/drivers/net/pcs/pcs-xpcs.c > @@ -695,9 +695,18 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs > *xpcs, > val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, > DW_VR_MII_PCS_MODE_C37_SGMII); > > - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { > - mask |= DW_VR_MII_AN_CTRL_8BIT; > + switch (xpcs->sgmii_10_100_8bit) { > + case DW_XPCS_SGMII_10_100_8BIT: > val |= DW_VR_MII_AN_CTRL_8BIT; > + fallthrough; > + case DW_XPCS_SGMII_10_100_4BIT: > + mask |= DW_VR_MII_AN_CTRL_8BIT; > + fallthrough; > + case DW_XPCS_SGMII_10_100_UNCHANGED: > + break; > + } > + > + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { > /* Hardware requires it to be PHY side SGMII */ > tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; > } else { > @@ -1450,10 +1459,12 @@ static struct dw_xpcs *xpcs_create(struct mdio_device > *mdiodev) > > xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); > > - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) > + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { > xpcs->pcs.poll = false; > - else > + xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT; > + } else { > xpcs->need_reset = true; > + } > > return xpcs; > > diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h > index adc5a0b3c883..4d53ccf917f3 100644 > --- a/drivers/net/pcs/pcs-xpcs.h > +++ b/drivers/net/pcs/pcs-xpcs.h > @@ -114,6 +114,12 @@ enum dw_xpcs_clock { > DW_XPCS_NUM_CLKS, > }; > > +enum dw_xpcs_sgmii_10_100 { > + DW_XPCS_SGMII_10_100_UNCHANGED, > + DW_XPCS_SGMII_10_100_4BIT, > + DW_XPCS_SGMII_10_100_8BIT > +}; > + > struct dw_xpcs { > struct dw_xpcs_info info; > const struct dw_xpcs_desc *desc; > @@ -122,6 +128,8 @@ struct dw_xpcs { > struct phylink_pcs pcs; > phy_interface_t interface; > bool need_reset; > + /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ > + enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit; > }; > > int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg); > -- Tested-by: Tristram Ha <tristram.ha@microchip.com>
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 1faa37f0e7b9..12a3d5a80b45 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -695,9 +695,18 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, val = FIELD_PREP(DW_VR_MII_PCS_MODE_MASK, DW_VR_MII_PCS_MODE_C37_SGMII); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { - mask |= DW_VR_MII_AN_CTRL_8BIT; + switch (xpcs->sgmii_10_100_8bit) { + case DW_XPCS_SGMII_10_100_8BIT: val |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_4BIT: + mask |= DW_VR_MII_AN_CTRL_8BIT; + fallthrough; + case DW_XPCS_SGMII_10_100_UNCHANGED: + break; + } + + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { /* Hardware requires it to be PHY side SGMII */ tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII; } else { @@ -1450,10 +1459,12 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev) xpcs_get_interfaces(xpcs, xpcs->pcs.supported_interfaces); - if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) + if (xpcs->info.pma == WX_TXGBE_XPCS_PMA_10G_ID) { xpcs->pcs.poll = false; - else + xpcs->sgmii_10_100_8bit = DW_XPCS_SGMII_10_100_8BIT; + } else { xpcs->need_reset = true; + } return xpcs; diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index adc5a0b3c883..4d53ccf917f3 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -114,6 +114,12 @@ enum dw_xpcs_clock { DW_XPCS_NUM_CLKS, }; +enum dw_xpcs_sgmii_10_100 { + DW_XPCS_SGMII_10_100_UNCHANGED, + DW_XPCS_SGMII_10_100_4BIT, + DW_XPCS_SGMII_10_100_8BIT +}; + struct dw_xpcs { struct dw_xpcs_info info; const struct dw_xpcs_desc *desc; @@ -122,6 +128,8 @@ struct dw_xpcs { struct phylink_pcs pcs; phy_interface_t interface; bool need_reset; + /* Width of the MII MAC/XPCS interface in 100M and 10M modes */ + enum dw_xpcs_sgmii_10_100 sgmii_10_100_8bit; }; int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
When in SGMII mode, the hardware can be configured to use either 4-bit or 8-bit MII connection. Currently, we don't change this bit for most implementations with the exception of TXGBE requiring 8-bit. Move this decision to the creation code and act on it when configuring SGMII. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> --- drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++++++---- drivers/net/pcs/pcs-xpcs.h | 8 ++++++++ 2 files changed, 23 insertions(+), 4 deletions(-)