From patchwork Tue Mar 4 10:53:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Russell King (Oracle)" X-Patchwork-Id: 14000432 X-Patchwork-Delegate: kuba@kernel.org Received: from pandora.armlinux.org.uk (pandora.armlinux.org.uk [78.32.30.218]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 039A51EE00A for ; Tue, 4 Mar 2025 10:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=78.32.30.218 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741085629; cv=none; b=q7p1D/6iqOZHnGpdmqj8DTGF3Z95+gHhtbXUh3Gow4DvEj0NzF5MavGeLLW3vJrOsZ9xf0Z8uklWkBYQD970uNV1VLERv43PsWfX0W/4x6tRFqjXk54C9a5e8sUoiWmZjX2t427dVdLfrZoHY7rLjMizTd+Ov3nj0EkgAn0zGLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741085629; c=relaxed/simple; bh=RMHHdXrRYsBBmTg9InHQdwXMQYXLJxWivLxWPAbGN2Y=; h=In-Reply-To:References:From:To:Cc:Subject:MIME-Version: Content-Disposition:Content-Type:Message-Id:Date; b=HafE7tZcd61nWVcp+G9uv4MInh+EMlJE1nKshu+lOLXWZWmNnGWv37ZlOlPHBG+meIIxESa4L6REEicQXgT2STxM1zbvCL8+pR/baltA6Gggs8y+3m51VMRIwhCaakXqBJMD5FwxsSpi1ZEmjDHhJ1xdzP6QPI2QxPvTo3Wro30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk; spf=none smtp.mailfrom=armlinux.org.uk; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b=FivH1/OB; arc=none smtp.client-ip=78.32.30.218 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=armlinux.org.uk Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=armlinux.org.uk header.i=@armlinux.org.uk header.b="FivH1/OB" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=armlinux.org.uk; s=pandora-2019; h=Date:Sender:Message-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Subject:Cc:To:From:References: In-Reply-To:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=ZNFqA3+Nw6GvLgCDAt36lni//r7MMRQPT9N/OXmnuW4=; b=FivH1/OBGc7gy5gzL+3Q7u+867 iLmMa3hIffL2Bl4INg87T+QtW9bV1B6GI557lP63Ae2bUkZHUPwYFFHPQwJuB91Djpc16NpX4drDF OP0VBGYGJiGfdIUzICNnPoWBM9FacD9rGR13x3bB/CAZFnjg2aZsyQdE96KtsTCCLkwEbX+Tc+S6o tGN29UMjz2j7gJba1UGVpCzcgcjK1CUqfOb1O07a0qaOY+ZUCdvsL40bNEVDvclS0rKM+xPacH2D2 ar3b/J0QypYvJnTew6hMRef5o5GhMCYmxPUccDTSAzIxav4fCf1C1EPtvwN1TxGUS9AYyO0Lu4tHH vceDHLKg==; Received: from e0022681537dd.dyn.armlinux.org.uk ([fd8f:7570:feb6:1:222:68ff:fe15:37dd]:34928 helo=rmk-PC.armlinux.org.uk) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tpPu9-0002Uh-0r; Tue, 04 Mar 2025 10:53:41 +0000 Received: from rmk by rmk-PC.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1tpPtp-005SoU-7N; Tue, 04 Mar 2025 10:53:21 +0000 In-Reply-To: References: From: "Russell King (Oracle)" To: Jon Hunter , Thierry Reding , "Lad, Prabhakar" Cc: Alexandre Torgue , Andrew Lunn , Andrew Lunn , "David S. Miller" , Eric Dumazet , Heiner Kallweit , Jakub Kicinski , linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Maxime Coquelin , netdev@vger.kernel.org, Paolo Abeni Subject: [PATCH RFC net-next 1/3] net: phylink: add config of PHY receive clock-stop in phylink_resume() Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Message-Id: Sender: Russell King Date: Tue, 04 Mar 2025 10:53:21 +0000 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Add configuration of the receive clock-stop in phylink_resume() to ensure that the clock-stop is correctly configured. Reviewed-by: Andrew Lunn Signed-off-by: Russell King (Oracle) --- drivers/net/phy/phylink.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index a3b186ab3854..0aae0bb2a254 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -2264,7 +2264,7 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, pl->mac_tx_clk_stop = phy_eee_tx_clock_stop_capable(phy) > 0; if (pl->mac_supports_eee_ops) { - /* Explicitly configure whether the PHY is allowed to stop it's + /* Explicitly configure whether the PHY is allowed to stop its * receive clock. */ ret = phy_eee_rx_clock_stop(phy, @@ -2645,8 +2645,22 @@ EXPORT_SYMBOL_GPL(phylink_suspend); */ void phylink_resume(struct phylink *pl) { + int ret; + ASSERT_RTNL(); + if (pl->mac_supports_eee_ops && pl->phydev) { + /* Explicitly configure whether the PHY is allowed to stop its + * receive clock on resume to ensure that it is correctly + * configured. + */ + ret = phy_eee_rx_clock_stop(pl->phydev, + pl->config->eee_rx_clk_stop_enable); + if (ret == -EOPNOTSUPP) + phylink_warn(pl, "failed to set rx clock stop: %pe\n", + ERR_PTR(ret)); + } + if (test_bit(PHYLINK_DISABLE_MAC_WOL, &pl->phylink_disable_state)) { /* Wake-on-Lan enabled, MAC handling */