From patchwork Wed Dec 6 01:43:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 13480955 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F1D91B2; Tue, 5 Dec 2023 17:44:13 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1rAgxC-0002ex-16; Wed, 06 Dec 2023 01:43:59 +0000 Date: Wed, 6 Dec 2023 01:43:55 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Qingfang Deng , SkyLake Huang , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH v2 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings Message-ID: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Patchwork-State: RFC Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes: * USXGMII * 10GBase-R * 5GBase-R * 2500Base-X * 1000Base-X * Cisco SGMII (MAC side) Signed-off-by: Daniel Golle --- .../bindings/phy/mediatek,xfi-pextp.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file mode 100644 index 0000000000000..58c93368141e2 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek XFI PEXTP SerDes PHY + +maintainers: + - Daniel Golle + +description: + The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes + used by the MediaTek USXGMII PCS. + +properties: + $nodename: + pattern: "^phy@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-xfi-pextp + + reg: + maxItems: 1 + + clocks: + items: + - description: XFI PHY clock + - description: XFI register clock + + clock-names: + items: + - const: "xfipll" + - const: "topxtal" + + resets: + items: + - description: PEXTP reset + + mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + clock-names = "xfipll", "topxtal"; + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + }; + +...