From patchwork Fri Oct 7 10:31:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajneesh Bhardwaj X-Patchwork-Id: 9365995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 46F2C60487 for ; Fri, 7 Oct 2016 10:32:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37C6A294C8 for ; Fri, 7 Oct 2016 10:32:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C6C2294CC; Fri, 7 Oct 2016 10:32:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E0BD294C8 for ; Fri, 7 Oct 2016 10:32:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755475AbcJGKbz (ORCPT ); Fri, 7 Oct 2016 06:31:55 -0400 Received: from mga09.intel.com ([134.134.136.24]:63784 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754598AbcJGKba (ORCPT ); Fri, 7 Oct 2016 06:31:30 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 07 Oct 2016 03:31:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,308,1473145200"; d="scan'208";a="1041598604" Received: from rajaneesh-optiplex-9010.iind.intel.com ([10.223.135.11]) by orsmga001.jf.intel.com with ESMTP; 07 Oct 2016 03:31:28 -0700 From: Rajneesh Bhardwaj To: platform-driver-x86@vger.kernel.org Cc: dvhart@infradead.org, andriy.shevchenko@linux.intel.com, linux-kernel@vger.kernel.org, Rajneesh Bhardwaj Subject: [PATCH v1 5/6] intel_pmc_core: Add LTR IGNORE debug feature Date: Fri, 7 Oct 2016 16:01:16 +0530 Message-Id: <1475836277-4788-6-git-send-email-rajneesh.bhardwaj@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1475836277-4788-1-git-send-email-rajneesh.bhardwaj@intel.com> References: <1475836277-4788-1-git-send-email-rajneesh.bhardwaj@intel.com> Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP SPT LTR_IGN register provides a means to make the PMC ignore the LTR values reported by the individual PCH devices. echo > /sys/kernel/debug/pmc_core/ltr_ignore. When a particular IP Offset bit is set the PMC will ignore the LTR value reported by the corresponding IP when the PMC performs the latency coalescing. IP Offset IP Name 0 SPA 1 SPB 2 SATA 3 GBE 4 XHCI 5 RSVD 6 ME 7 EVA 8 SPC 9 Azalia/ADSP 10 RSVD 11 LPSS 12 SPD 13 SPE 14 Camera 15 ESPI 16 SCC 17 ISH Signed-off-by: Rajneesh Bhardwaj --- drivers/platform/x86/intel_pmc_core.c | 57 ++++++++++++++++++++++++++++++++++- drivers/platform/x86/intel_pmc_core.h | 2 ++ 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 4840158..5b867b7 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -19,11 +19,12 @@ */ #include +#include #include #include #include #include -#include +#include #include #include @@ -373,6 +374,53 @@ static const struct file_operations pmc_core_pll_ops = { .release = single_release, }; +static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user +*userbuf, size_t count, loff_t *ppos) +{ + u32 val, buf_size, fd; + int err = 0; + struct pmc_dev *pmcdev = &pmc; + + buf_size = count < 64 ? count : 64; + mutex_lock(&pmcdev->lock); + + if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) { + err = -EFAULT; + goto out_unlock; + } + + if (val > NUM_IP_IGN_ALLOWED) { + err = -EINVAL; + goto out_unlock; + } + + fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET); + fd |= (1U << val); + pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd); + +out_unlock: + mutex_unlock(&pmcdev->lock); + return err == 0 ? count : err; +} + +static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused) +{ + return 0; +} + +static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file) +{ + return single_open(file, pmc_core_ltr_ignore_show, inode->i_private); +} + +static const struct file_operations pmc_core_ltr_ignore_ops = { + .open = pmc_core_ltr_ignore_open, + .read = seq_read, + .write = pmc_core_ltr_ignore_write, + .llseek = seq_lseek, + .release = single_release, +}; + static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) { debugfs_remove_recursive(pmcdev->dbgfs_dir); @@ -410,6 +458,13 @@ static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev) if (!file) goto err; + file = debugfs_create_file("ltr_ignore", + S_IFREG | S_IRUGO, dir, pmcdev, + &pmc_core_ltr_ignore_ops); + + if (!file) + goto err; + return 0; err: pmc_core_dbgfs_unregister(pmcdev); diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 07161fb..5a48e77 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -30,6 +30,7 @@ #define SPT_PMC_PM_STS_OFFSET 0x1c #define SPT_PMC_MTPMC_OFFSET 0x20 #define SPT_PMC_MFPMC_OFFSET 0x38 +#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C #define SPT_PMC_MPHY_CORE_STS_0 0x1143 #define SPT_PMC_MPHY_CORE_STS_1 0x1142 #define SPT_PMC_MPHY_COM_STS_0 0x1155 @@ -41,6 +42,7 @@ #define SPT_PMC_READ_DISABLE_BIT 0x16 #define SPT_PMC_MSG_FULL_STS_BIT 0x18 #define NUM_RETRIES 100 +#define NUM_IP_IGN_ALLOWED 17 /* Sunrise Point: PGD PFET Enable Ack Status Registers */ enum ppfear_regs {