From patchwork Fri Feb 17 09:23:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajneesh Bhardwaj X-Patchwork-Id: 9579273 X-Patchwork-Delegate: andy.shevchenko@gmail.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 863AF6049F for ; Fri, 17 Feb 2017 09:24:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7E46D28675 for ; Fri, 17 Feb 2017 09:24:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 711FC2868A; Fri, 17 Feb 2017 09:24:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D89B928675 for ; Fri, 17 Feb 2017 09:24:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932452AbdBQJYF (ORCPT ); Fri, 17 Feb 2017 04:24:05 -0500 Received: from mga05.intel.com ([192.55.52.43]:47106 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756020AbdBQJX5 (ORCPT ); Fri, 17 Feb 2017 04:23:57 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP; 17 Feb 2017 01:23:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,171,1484035200"; d="scan'208";a="823925345" Received: from unknown (HELO rajaneesh-OptiPlex-9010.iind.intel.com) ([10.223.107.31]) by FMSMGA003.fm.intel.com with ESMTP; 17 Feb 2017 01:23:55 -0800 From: Rajneesh Bhardwaj To: platform-driver-x86@vger.kernel.org Cc: dvhart@infradead.org, andriy.shevchenko@linux.intel.com, linux-kernel@vger.kernel.org, Rajneesh Bhardwaj Subject: [PATCH] platform/x86: intel_pmc_ipc: Use XTAL freq based on cpuid Date: Fri, 17 Feb 2017 14:53:54 +0530 Message-Id: <1487323434-8553-1-git-send-email-rajneesh.bhardwaj@intel.com> X-Mailer: git-send-email 1.9.1 Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch uses crystal frequency based on the cpu model. On Apollo Lake SoC we have 19.2 MHz clock frequency for counting S0ix residency but this clock frequency might change on future platforms depending on the crystal oscillator. Signed-off-by: Shanth Murthy Signed-off-by: Rajneesh Bhardwaj --- Note: This patch depends on the following: * platform/x86: intel_pmc_ipc: read s0ix residency API * platform/x86: intel_pmc_ipc: Add APL PMC PCI Id drivers/platform/x86/intel_pmc_ipc.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 6b6bdf1..557f017 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -34,6 +34,7 @@ #include #include +#include #include #include @@ -61,11 +62,11 @@ #define GCR_TELEM_DEEP_S0IX_OFFSET 0x1078 #define GCR_TELEM_SHLW_S0IX_OFFSET 0x1080 -/* Residency with clock rate at 19.2MHz to usecs */ -#define S0IX_RESIDENCY_IN_USECS(d, s) \ +/* Convert S0ix residency to usecs based on XTAL frequency */ +#define S0IX_RESIDENCY_IN_USECS(d, s, x) \ ({ \ - u64 result = 10ull * ((d) + (s)); \ - do_div(result, 192); \ + u64 result = 1000ull * ((d) + (s)); \ + do_div(result, x); \ result; \ }) @@ -131,6 +132,7 @@ resource_size_t gcr_base; int gcr_size; bool has_gcr_regs; + u32 xtal_khz; /* punit */ struct platform_device *punit_dev; @@ -201,6 +203,18 @@ static inline u64 gcr_data_readq(u32 offset) return readq(ipcdev.ipc_base + offset); } +static int get_xtal_clock_freq(void) +{ + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_ATOM_GOLDMONT: + ipcdev.xtal_khz = 19200; + break; + default: + return -EINVAL; + } + return 0; +} + static int intel_pmc_ipc_check_status(void) { int status; @@ -787,7 +801,7 @@ int intel_pmc_s0ix_counter_read(u64 *data) deep = gcr_data_readq(GCR_TELEM_DEEP_S0IX_OFFSET); shlw = gcr_data_readq(GCR_TELEM_SHLW_S0IX_OFFSET); - *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); + *data = S0IX_RESIDENCY_IN_USECS(deep, shlw, ipcdev.xtal_khz); return 0; } @@ -835,6 +849,12 @@ static int ipc_plat_probe(struct platform_device *pdev) goto err_irq; } + ret = get_xtal_clock_freq(); + if (ret) { + dev_err(&pdev->dev, "Failed to get XTAL freq\n"); + goto err_sys; + } + ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group); if (ret) { dev_err(&pdev->dev, "Failed to create sysfs group %d\n",