From patchwork Tue Nov 21 14:36:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chakravarty, Souvik K" X-Patchwork-Id: 10067693 X-Patchwork-Delegate: andy.shevchenko@gmail.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ED1DA6022E for ; Tue, 21 Nov 2017 06:31:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1E6B28D8E for ; Tue, 21 Nov 2017 06:31:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D5B9928D95; Tue, 21 Nov 2017 06:31:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89D9728D8E for ; Tue, 21 Nov 2017 06:31:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752960AbdKUGaW (ORCPT ); Tue, 21 Nov 2017 01:30:22 -0500 Received: from mga06.intel.com ([134.134.136.31]:21621 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752949AbdKUGaU (ORCPT ); Tue, 21 Nov 2017 01:30:20 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Nov 2017 22:30:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,432,1505804400"; d="scan'208";a="1246702000" Received: from skchakra-desk-3.iind.intel.com ([10.66.254.101]) by fmsmga002.fm.intel.com with ESMTP; 20 Nov 2017 22:30:18 -0800 From: Souvik Kumar Chakravarty To: platform-driver-x86@vger.kernel.org Cc: dvhart@infradead.org, andy@infradead.org, linux-kernel@vger.kernel.org, rajneesh.bhardwaj@intel.com, Souvik Kumar Chakravarty Subject: [PATCH v1 1/4] platform/x86: intel_pmc_ipc: Add readq API for GCR Date: Tue, 21 Nov 2017 20:06:21 +0530 Message-Id: <1511274984-6165-2-git-send-email-souvik.k.chakravarty@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1511274984-6165-1-git-send-email-souvik.k.chakravarty@intel.com> References: <1511274984-6165-1-git-send-email-souvik.k.chakravarty@intel.com> Sender: platform-driver-x86-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add intel_pmc_gcr_readq API for reading from 64-bit GCR registers. This API will be called from intel_telemetry. Rename intel_pmc_gcr_read to more appropriate intel_pmc_gcr_readl. Signed-off-by: Souvik Kumar Chakravarty --- arch/x86/include/asm/intel_pmc_ipc.h | 10 ++++++++-- drivers/platform/x86/intel_pmc_ipc.c | 37 ++++++++++++++++++++++++++++++++---- 2 files changed, 41 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index fac89eb..0aa5be9 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -36,7 +36,8 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, u32 outlen); int intel_pmc_s0ix_counter_read(u64 *data); -int intel_pmc_gcr_read(u32 offset, u32 *data); +int intel_pmc_gcr_readl(u32 offset, u32 *data); +int intel_pmc_gcr_readq(u32 offset, u64 *data); int intel_pmc_gcr_write(u32 offset, u32 data); int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); @@ -64,7 +65,12 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data) return -EINVAL; } -static inline int intel_pmc_gcr_read(u32 offset, u32 *data) +static inline int intel_pmc_gcr_readl(u32 offset, u32 *data) +{ + return -EINVAL; +} + +static inline int intel_pmc_gcr_readq(u32 offset, u64 *data) { return -EINVAL; } diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index e03fa314..bef9c57 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -215,15 +215,15 @@ static inline int is_gcr_valid(u32 offset) } /** - * intel_pmc_gcr_read() - Read PMC GCR register + * intel_pmc_gcr_readl() - Read a 32-bit PMC GCR register * @offset: offset of GCR register from GCR address base * @data: data pointer for storing the register output * - * Reads the PMC GCR register of given offset. + * Reads the 32-bit PMC GCR register at given offset. * * Return: negative value on error or 0 on success. */ -int intel_pmc_gcr_read(u32 offset, u32 *data) +int intel_pmc_gcr_readl(u32 offset, u32 *data) { int ret; @@ -241,7 +241,36 @@ int intel_pmc_gcr_read(u32 offset, u32 *data) return 0; } -EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); +EXPORT_SYMBOL_GPL(intel_pmc_gcr_readl); + +/** + * intel_pmc_gcr_readq() - Read a 64-bit PMC GCR register + * @offset: offset of GCR register from GCR address base + * @data: data pointer for storing the register output + * + * Reads the 64-bit PMC GCR register at given offset. + * + * Return: negative value on error or 0 on success. + */ +int intel_pmc_gcr_readq(u32 offset, u64 *data) +{ + int ret; + + spin_lock(&ipcdev.gcr_lock); + + ret = is_gcr_valid(offset); + if (ret < 0) { + spin_unlock(&ipcdev.gcr_lock); + return ret; + } + + *data = readq(ipcdev.gcr_mem_base + offset); + + spin_unlock(&ipcdev.gcr_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pmc_gcr_readq); /** * intel_pmc_gcr_write() - Write PMC GCR register