| Message ID | 20190213150810.32750-7-rajneesh.bhardwaj@linux.intel.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | ICL support and other enhancements for PMC Core | expand |
On Wed, Feb 13, 2019 at 08:38:06PM +0530, Rajneesh Bhardwaj wrote: > Add CPUID of Icelake (ICL) mobile processors to Intel family list. The > information related to ICL CPUID is referenced from below Coreboot > project link. > > https://github.com/coreboot/coreboot/blob/5ebcea3aaaa3cd358bc5bccaa156b13a6ef25df6/src/soc/intel/common/block/include/intelblocks/mp_init.h > I believe tglx was suggesting you should drop this link. If you can't reference an official document, then you don't need any reference.
On 13-Feb-19 8:53 PM, Borislav Petkov wrote: > On Wed, Feb 13, 2019 at 08:38:06PM +0530, Rajneesh Bhardwaj wrote: >> Add CPUID of Icelake (ICL) mobile processors to Intel family list. The >> information related to ICL CPUID is referenced from below Coreboot >> project link. >> >> https://github.com/coreboot/coreboot/blob/5ebcea3aaaa3cd358bc5bccaa156b13a6ef25df6/src/soc/intel/common/block/include/intelblocks/mp_init.h >> > I believe tglx was suggesting you should drop this link. If you can't > reference an official document, then you don't need any reference. Icelake related information is available here https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html but it may require a login either with Intel or a Partner ID. The CPUID mentioned in this document is 0x706E0 which is same as per this coreboot link. >
On Wed, Feb 13, 2019 at 09:13:01PM +0530, Bhardwaj, Rajneesh wrote: > Icelake related information is available here https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html > but it may require a login either with Intel or a Partner ID. > > The CPUID mentioned in this document is 0x706E0 which is same as per this > coreboot link. You did not read what I wrote.
I sure did, perhaps it wasn't clear in my response. I can remove coreboot link in next version but please clarify whether i should keep other link that i mentioned or just keep the commit without any link? On 13-Feb-19 9:34 PM, Borislav Petkov wrote: > On Wed, Feb 13, 2019 at 09:13:01PM +0530, Bhardwaj, Rajneesh wrote: >> Icelake related information is available here https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html >> but it may require a login either with Intel or a Partner ID. >> >> The CPUID mentioned in this document is 0x706E0 which is same as per this >> coreboot link. > You did not read what I wrote. >
On 2/13/19 8:35 AM, Bhardwaj, Rajneesh wrote: > I sure did, perhaps it wasn't clear in my response. I can remove > coreboot link in next version but please clarify whether i should keep > other link that i mentioned or just keep the commit without any link? I think we're hearing loud and clear from the maintainers that they prefer *public*, official documentation from Intel to back up our patches. Barring that, they'd rather have no link than a link to some other random project.
On 13-Feb-19 10:10 PM, Dave Hansen wrote: > On 2/13/19 8:35 AM, Bhardwaj, Rajneesh wrote: >> I sure did, perhaps it wasn't clear in my response. I can remove >> coreboot link in next version but please clarify whether i should keep >> other link that i mentioned or just keep the commit without any link? > I think we're hearing loud and clear from the maintainers that they > prefer *public*, official documentation from Intel to back up our patches. > > Barring that, they'd rather have no link than a link to some other > random project. Thank you Dave for the clarification. Hi Borislav, I realize that the link i mentioned is not public. Apologies for creating confusion around that and for the previous top posting. I will drop references to the coreboot link too in the next version. >
On Wed, Feb 13, 2019 at 10:43:30PM +0530, Bhardwaj, Rajneesh wrote: > Hi Borislav, I realize that the link i mentioned is not public. Apologies > for creating confusion around that and for the previous top posting. I will > drop references to the coreboot link too in the next version. As we talked on IRC with Dave, those patches don't need to point to an official document. If the model number is wrong, we'll learn very soon about it. :-) If it is a patchset enabling a feature or an erratum, then this becomes a whole different story. Thx.
diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index d9a9993af882..9f15384c504a 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -52,6 +52,8 @@ #define INTEL_FAM6_CANNONLAKE_MOBILE 0x66 +#define INTEL_FAM6_ICELAKE_MOBILE 0x7E + /* "Small Core" Processors (Atom) */ #define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
Add CPUID of Icelake (ICL) mobile processors to Intel family list. The information related to ICL CPUID is referenced from below Coreboot project link. https://github.com/coreboot/coreboot/blob/5ebcea3aaaa3cd358bc5bccaa156b13a6ef25df6/src/soc/intel/common/block/include/intelblocks/mp_init.h Cc: x86@kernel.org Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> --- arch/x86/include/asm/intel-family.h | 2 ++ 1 file changed, 2 insertions(+)