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David Alan Gilbert" , , , , , Brijesh Singh Subject: [PATCH v11 09/45] x86/mm: Extend cc_attr to include AMD SEV-SNP Date: Thu, 24 Feb 2022 10:55:49 -0600 Message-ID: <20220224165625.2175020-10-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224165625.2175020-1-brijesh.singh@amd.com> References: <20220224165625.2175020-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: df51d1dc-6cc9-4c71-898a-08d9f7b6dbc2 X-MS-TrafficTypeDiagnostic: BN8PR12MB4626:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dIVl0z9f8WA/oC9j+MmtJ3rLrL2NyWmi6CDI2fZmrz4daUIGyC1JZRJGh82JqnClGp2+8OkWj9yI+D9vZQLzCrsyTRejhHtbWRhcGEt6MxdOZVJV2zdHROyReWaoPHZYBUZLMe2U2yuOjAOGeyaHzljOUQnaeoD0DUn4f3koAaqB9Mj/DNAW0jY5U+/JL/tYmkABYShqputa/1/+cEe/VgLn50wN1hy/T8DdA28fdWk8ABeFe1r3jwVbKIhR/R0fcWcD2pXrKJyiK8GufbS17uOHbw4tNOOZpTq0od74MctT0qgj0VJZRkIJO59Lo6YBbbNJwKZVwI00VkNuM7+Y6MDdn6oeDkxwsMH2FpbaYEYFGg3P5BBrxTwePrZOAAQ5p2xRO+jxvBz23kHiP8RrbgQm6Rpyp5uaFyQPdDIua1f7jnKNPbufSo7Dn5NXDs5YLPpwzBEH+XbexwqpLbEUH8FAHFbfpk3Ih16NoWXc9pVobMRjaFBGvJub5Xn/1gQTZ+CQxfVLGQwwlhl04tYe2nKjXK9l3JDufzGu7wgDC9lMhog15YSO0La7zOEovYyydJftyTn+bc5IcQr0NeMIKFFyWJa8JpCBekQAPWrmzjhjWQTTL1shve1nmToyezZl0452iMNKWdQp1QbgB6CVd5iuIot59DBjKJjtQJQN54UPIJCZMi3ClHLCuYBOakiJaTBpDVyYmXH8JpwXh4VtS4wYZWKEwKiUol9o7Lokugs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(47076005)(36756003)(82310400004)(7696005)(508600001)(6666004)(40460700003)(356005)(7406005)(7416002)(70206006)(8936002)(36860700001)(81166007)(54906003)(186003)(70586007)(4326008)(44832011)(16526019)(2906002)(2616005)(426003)(316002)(8676002)(110136005)(5660300002)(86362001)(336012)(1076003)(26005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2022 16:58:19.1610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df51d1dc-6cc9-4c71-898a-08d9f7b6dbc2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4626 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org The CC_ATTR_GUEST_SEV_SNP can be used by the guest to query whether the SNP (Secure Nested Paging) feature is active. Signed-off-by: Brijesh Singh --- arch/x86/coco/core.c | 3 +++ arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/mm/mem_encrypt.c | 4 ++++ include/linux/cc_platform.h | 8 ++++++++ 4 files changed, 17 insertions(+) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index fc1365dd927e..dafd4881ce29 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -57,6 +57,9 @@ static bool amd_cc_platform_has(enum cc_attr attr) return (sev_status & MSR_AMD64_SEV_ENABLED) && !(sev_status & MSR_AMD64_SEV_ES_ENABLED); + case CC_ATTR_GUEST_SEV_SNP: + return sev_status & MSR_AMD64_SEV_SNP_ENABLED; + default: return false; } diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a142cab6882e..1315531e66ef 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -484,8 +484,10 @@ #define MSR_AMD64_SEV 0xc0010131 #define MSR_AMD64_SEV_ENABLED_BIT 0 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 +#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) +#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 50d209939c66..f85868c031c6 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -62,6 +62,10 @@ static void print_mem_encrypt_feature_info(void) if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) pr_cont(" SEV-ES"); + /* Secure Nested Paging */ + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) + pr_cont(" SEV-SNP"); + pr_cont("\n"); } diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index efd8205282da..d08dd65b5c43 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -72,6 +72,14 @@ enum cc_attr { * Examples include TDX guest & SEV. */ CC_ATTR_GUEST_UNROLL_STRING_IO, + + /** + * @CC_ATTR_SEV_SNP: Guest SNP is active. + * + * The platform/OS is running as a guest/virtual machine and actively + * using AMD SEV-SNP features. + */ + CC_ATTR_GUEST_SEV_SNP, }; #ifdef CONFIG_ARCH_HAS_CC_PLATFORM