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David Alan Gilbert" , , , , , Brijesh Singh Subject: [PATCH v12 09/46] x86/mm: Extend cc_attr to include AMD SEV-SNP Date: Mon, 7 Mar 2022 15:33:19 -0600 Message-ID: <20220307213356.2797205-10-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220307213356.2797205-1-brijesh.singh@amd.com> References: <20220307213356.2797205-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8aa8f56a-1457-428d-abaf-08da0082489f X-MS-TrafficTypeDiagnostic: MN0PR12MB5763:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HGWg9PUnbg9xa9OjB5R1rnsyc9DTftLwVkVyt9qp6wsKpGPDTbALncQ4Qu8Jkgmri+QimEDctdCFT6HW5v+FDjOfsobXW57l1BvQNoXNgH531MJdiDEZ8qTRXXyM7clXWDftFJgAc5CsbY0uGRS5jqHlXu9ulfDrEAihVEeFrhLJp4iWl0KfLPyi5dl02Av2FjN7n5sOjlG10+MRhvjo90eWUugMOgWDtQStahGSJTCvFN0Z/oGY5JyVRj/vrUnQewcxokzjXdUn8pw4wmmDExP3jfEMOUIaPNR89cI1XXa7frMrvsbQ7Dkx/WTx9YCkkWAPQbrWN51gMRnFgS/AtmHhYzYrjc8X6Gm1FyNCHB7Rjhms49vSf+r0AmtRIcxSuFbngpC40Zr06eLogQeyx+P8NnHKCIU7/sFeS8hAz7mJta8SuMRW34M9VQxMkgq1L0J2Xp6nbipngmDp4lEq2j07at7w+tXarfN8RVx7t9n7JI/XDGRLVWr4xGKaMq1D9Sp8+AABiTrQk7wV7e7kf/1p34BVgJnVB7q+o7pA3EVTwMpxP9jZSXMb3vLcwSE3mn+nzzmZTCrm8Wq6wr+ZQbdJnwrRdd+fSnuL3ftaevRg93V/0grFVydhL15LbvIc26akxUM4T0SgZ/cnoMUdomTbWT44VMKBc5DoFY0fOd2W83s0HMAbvXjq1WTFNbbWhdwBusQjBiNkuf3LgEHYVO/kp6sRsceOax/PEaUw+Ks= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(8676002)(356005)(508600001)(70206006)(2616005)(16526019)(70586007)(4326008)(86362001)(8936002)(6666004)(426003)(1076003)(47076005)(336012)(186003)(40460700003)(26005)(36756003)(7696005)(7416002)(5660300002)(7406005)(81166007)(316002)(110136005)(54906003)(44832011)(82310400004)(2906002)(36860700001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Mar 2022 21:34:38.9737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8aa8f56a-1457-428d-abaf-08da0082489f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5763 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org The CC_ATTR_GUEST_SEV_SNP can be used by the guest to query whether the SNP (Secure Nested Paging) feature is active. Signed-off-by: Brijesh Singh --- arch/x86/coco/core.c | 3 +++ arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/mm/mem_encrypt.c | 4 ++++ include/linux/cc_platform.h | 8 ++++++++ 4 files changed, 17 insertions(+) diff --git a/arch/x86/coco/core.c b/arch/x86/coco/core.c index fc1365dd927e..dafd4881ce29 100644 --- a/arch/x86/coco/core.c +++ b/arch/x86/coco/core.c @@ -57,6 +57,9 @@ static bool amd_cc_platform_has(enum cc_attr attr) return (sev_status & MSR_AMD64_SEV_ENABLED) && !(sev_status & MSR_AMD64_SEV_ES_ENABLED); + case CC_ATTR_GUEST_SEV_SNP: + return sev_status & MSR_AMD64_SEV_SNP_ENABLED; + default: return false; } diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a142cab6882e..1315531e66ef 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -484,8 +484,10 @@ #define MSR_AMD64_SEV 0xc0010131 #define MSR_AMD64_SEV_ENABLED_BIT 0 #define MSR_AMD64_SEV_ES_ENABLED_BIT 1 +#define MSR_AMD64_SEV_SNP_ENABLED_BIT 2 #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) +#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 50d209939c66..f85868c031c6 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -62,6 +62,10 @@ static void print_mem_encrypt_feature_info(void) if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) pr_cont(" SEV-ES"); + /* Secure Nested Paging */ + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) + pr_cont(" SEV-SNP"); + pr_cont("\n"); } diff --git a/include/linux/cc_platform.h b/include/linux/cc_platform.h index efd8205282da..d08dd65b5c43 100644 --- a/include/linux/cc_platform.h +++ b/include/linux/cc_platform.h @@ -72,6 +72,14 @@ enum cc_attr { * Examples include TDX guest & SEV. */ CC_ATTR_GUEST_UNROLL_STRING_IO, + + /** + * @CC_ATTR_SEV_SNP: Guest SNP is active. + * + * The platform/OS is running as a guest/virtual machine and actively + * using AMD SEV-SNP features. + */ + CC_ATTR_GUEST_SEV_SNP, }; #ifdef CONFIG_ARCH_HAS_CC_PLATFORM