From patchwork Mon Aug 1 11:30:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 12933701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D71B0C00144 for ; Mon, 1 Aug 2022 11:30:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230202AbiHALaP (ORCPT ); Mon, 1 Aug 2022 07:30:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229815AbiHALaO (ORCPT ); Mon, 1 Aug 2022 07:30:14 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F29EE56; Mon, 1 Aug 2022 04:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659353413; x=1690889413; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=a61lpXtFRcD7rCy0IlruL3g3efXxumVvdinkbqWTrRw=; b=PqTiIoHNzwSUDQU+6gyCj9go+IbQr5PBo+u2KyPdufCPrfgP8KQkytVl ll5X3eqhZnMiGmTCc0BO1KMFERZSgOU5kf7GVrKMiKK/q2C1WT+P99KRL JGvsKJKtOfdRk9iNPkuGILd4/jfTBWywLy06QeHlCN6FLmzdedBCpyMfP pFPump3Y796chP+pUqHTxeDfq4bqOsJ4KSIhI6ddURruizlY0oKe5QxOI mqD8ClRH0geGgWnRQZQQg7H+zwIFn5UUz9q2rtjo6D48RwS4yctCwtSMK JcIUyCGvJygeBdOkVTx0WcLRoO9HtUBTp53uIfaV0SkoJqRGKLsj8hQui Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10425"; a="276024209" X-IronPort-AV: E=Sophos;i="5.93,206,1654585200"; d="scan'208";a="276024209" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2022 04:30:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,206,1654585200"; d="scan'208";a="634860829" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga001.jf.intel.com with ESMTP; 01 Aug 2022 04:30:11 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id F2C8BF7; Mon, 1 Aug 2022 14:30:21 +0300 (EEST) From: Andy Shevchenko To: Hans de Goede , Andy Shevchenko , platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mark Gross Subject: [PATCH v1 1/4] platform/x86: pmc_atom: Fix SLP_TYPx bitfield mask Date: Mon, 1 Aug 2022 14:30:15 +0300 Message-Id: <20220801113018.9882-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org On Intel hardware the SLP_TYPx bitfield occupies bits 10-12 as per ACPI specification (see Table 4.13 "PM1 Control Registers Fixed Hardware Feature Control Bits" for the details). Fix the mask and other related definitions accordingly. Fixes: 93e5eadd1f6e ("x86/platform: New Intel Atom SOC power management controller driver") Signed-off-by: Andy Shevchenko --- drivers/platform/x86/pmc_atom.c | 2 +- include/linux/platform_data/x86/pmc_atom.h | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/platform/x86/pmc_atom.c b/drivers/platform/x86/pmc_atom.c index b8b1ed1406de..c220172fefbb 100644 --- a/drivers/platform/x86/pmc_atom.c +++ b/drivers/platform/x86/pmc_atom.c @@ -232,7 +232,7 @@ static void pmc_power_off(void) pm1_cnt_port = acpi_base_addr + PM1_CNT; pm1_cnt_value = inl(pm1_cnt_port); - pm1_cnt_value &= SLEEP_TYPE_MASK; + pm1_cnt_value &= ~SLEEP_TYPE_MASK; pm1_cnt_value |= SLEEP_TYPE_S5; pm1_cnt_value |= SLEEP_ENABLE; diff --git a/include/linux/platform_data/x86/pmc_atom.h b/include/linux/platform_data/x86/pmc_atom.h index 6807839c718b..1fee5d85f75d 100644 --- a/include/linux/platform_data/x86/pmc_atom.h +++ b/include/linux/platform_data/x86/pmc_atom.h @@ -7,6 +7,8 @@ #ifndef PMC_ATOM_H #define PMC_ATOM_H +#include + /* ValleyView Power Control Unit PCI Device ID */ #define PCI_DEVICE_ID_VLV_PMC 0x0F1C /* CherryTrail Power Control Unit PCI Device ID */ @@ -139,9 +141,9 @@ #define ACPI_MMIO_REG_LEN 0x100 #define PM1_CNT 0x4 -#define SLEEP_TYPE_MASK 0xFFFFECFF +#define SLEEP_TYPE_MASK GENMASK(12, 10) #define SLEEP_TYPE_S5 0x1C00 -#define SLEEP_ENABLE 0x2000 +#define SLEEP_ENABLE BIT(13) extern int pmc_atom_read(int offset, u32 *value);