From patchwork Tue Feb 14 23:44:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Joseph, Jithu" X-Patchwork-Id: 13141039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15EB2C61DA4 for ; Tue, 14 Feb 2023 23:46:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbjBNXp7 (ORCPT ); Tue, 14 Feb 2023 18:45:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232636AbjBNXp6 (ORCPT ); Tue, 14 Feb 2023 18:45:58 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D1892FCCA; Tue, 14 Feb 2023 15:45:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676418357; x=1707954357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SsjAevpmZdqyiSpl1ArywIOY8BazdttWbu087eKG+/g=; b=dkEoM+GoAyRFZo0rvisTTUjTD0yA6SyyRqYGhnwPlW/jQXIElQsqD0Dw XVYqKYimcndpYejJf7LMSm/aqqD9rYnh38rVOMSjOZjtPbmUFAV03YOeY JCCByYYzIUQj6XuLVlmQ2y0/mU6mp0mFjQMp9F8MXEzFT98LwcEFGbW4Q mV3y9Nr2ecaODInvdUHchJCqEyrxDrOwBqowvWdfES1/9UUN8R3mwtOXE TK4i5QL1b+rhbU2PTelaYrUXaPrU0UTbstgyQTNFlTL+xaYSaMG9Ml8zF 66RooV7XYHZI+ONZSMd+rAPzMCoOYY8eoDzqnMEClxF24cKQpJAUO1hUs Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="417523025" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="417523025" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:56 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="669391017" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="669391017" Received: from jithujos.sc.intel.com ([172.25.103.66]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:56 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH v2 4/7] platform/x86/intel/ifs: Implement Array BIST test Date: Tue, 14 Feb 2023 15:44:23 -0800 Message-Id: <20230214234426.344960-5-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214234426.344960-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> <20230214234426.344960-1-jithu.joseph@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: platform-driver-x86@vger.kernel.org Array BIST test (for a particlular core) is triggered by writing to MSR_ARRAY_BIST from one sibling of the core. This will initiate a test for all supported arrays on that CPU. Array BIST test may be aborted before completing all the arrays in the event of an interrupt or other reasons. In this case, kernel will restart the test from that point onwards. Array test will also be aborted when the test fails, in which case the test is stopped immediately without further retry. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- drivers/platform/x86/intel/ifs/ifs.h | 12 ++++ drivers/platform/x86/intel/ifs/runtest.c | 90 ++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/drivers/platform/x86/intel/ifs/ifs.h b/drivers/platform/x86/intel/ifs/ifs.h index a0cb2696c1d9..e5375191b56d 100644 --- a/drivers/platform/x86/intel/ifs/ifs.h +++ b/drivers/platform/x86/intel/ifs/ifs.h @@ -127,6 +127,7 @@ #include #include +#define MSR_ARRAY_BIST 0x00000105 #define MSR_COPY_SCAN_HASHES 0x000002c2 #define MSR_SCAN_HASHES_STATUS 0x000002c3 #define MSR_AUTHENTICATE_AND_COPY_CHUNK 0x000002c4 @@ -194,6 +195,17 @@ union ifs_status { }; }; +/* MSR_ARRAY_BIST bit fields */ +union ifs_array { + u64 data; + struct { + u32 array_bitmask :32; + u32 array_bank :16; + u32 rsvd :15; + u32 ctrl_result :1; + }; +}; + /* * Driver populated error-codes * 0xFD: Test timed out before completing all the chunks. diff --git a/drivers/platform/x86/intel/ifs/runtest.c b/drivers/platform/x86/intel/ifs/runtest.c index 65e08af70994..12880fca0aa8 100644 --- a/drivers/platform/x86/intel/ifs/runtest.c +++ b/drivers/platform/x86/intel/ifs/runtest.c @@ -229,6 +229,94 @@ static void ifs_test_core(int cpu, struct device *dev) } } +#define SPINUNIT 100 /* 100 nsec */ +static atomic_t array_cpus_out; + +/* + * Simplified cpu sibling rendezvous loop based on microcode loader __wait_for_cpus() + */ +static void wait_for_sibling_cpu(atomic_t *t, long long timeout) +{ + int cpu = smp_processor_id(); + const struct cpumask *smt_mask = cpu_smt_mask(cpu); + int all_cpus = cpumask_weight(smt_mask); + + atomic_inc(t); + while (atomic_read(t) < all_cpus) { + if (timeout < SPINUNIT) + return; + ndelay(SPINUNIT); + timeout -= SPINUNIT; + touch_nmi_watchdog(); + } +} + +static int do_array_test(void *data) +{ + int cpu = smp_processor_id(); + u64 *msrs = data; + int first; + + /* + * Only one logical CPU on a core needs to trigger the Array test via MSR write. + */ + first = cpumask_first(cpu_smt_mask(cpu)); + + if (cpu == first) { + wrmsrl(MSR_ARRAY_BIST, msrs[0]); + /* Pass back the result of the test */ + rdmsrl(MSR_ARRAY_BIST, msrs[1]); + } + + /* Tests complete faster if the sibling is spinning here */ + wait_for_sibling_cpu(&array_cpus_out, NSEC_PER_SEC); + + return 0; +} + +static void ifs_array_test_core(int cpu, struct device *dev) +{ + union ifs_array activate, status = {0}; + bool timed_out = false; + struct ifs_data *ifsd; + unsigned long timeout; + u64 msrvals[2]; + + ifsd = ifs_get_data(dev); + + activate.array_bitmask = ~0U; + timeout = jiffies + HZ / 2; + + do { + if (time_after(jiffies, timeout)) { + timed_out = true; + break; + } + + msrvals[0] = activate.data; + + atomic_set(&array_cpus_out, 0); + stop_core_cpuslocked(cpu, do_array_test, msrvals); + status.data = msrvals[1]; + + if (status.ctrl_result) + break; + + activate.array_bitmask = status.array_bitmask; + activate.array_bank = status.array_bank; + + } while (status.array_bitmask); + + ifsd->scan_details = status.data; + + if (status.ctrl_result) + ifsd->status = SCAN_TEST_FAIL; + else if (timed_out || status.array_bitmask) + ifsd->status = SCAN_NOT_TESTED; + else + ifsd->status = SCAN_TEST_PASS; +} + /* * Initiate per core test. It wakes up work queue threads on the target cpu and * its sibling cpu. Once all sibling threads wake up, the scan test gets executed and @@ -253,6 +341,8 @@ int do_core_test(int cpu, struct device *dev) ifs_test_core(cpu, dev); break; case IFS_ARRAY: + ifs_array_test_core(cpu, dev); + break; default: return -EINVAL; }