From patchwork Mon Jul 1 14:17:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael J. Ruhl" X-Patchwork-Id: 13718201 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1EBC161305 for ; Mon, 1 Jul 2024 14:17:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719843477; cv=none; b=jPcUsv7Jc8ZD0n819RAqirEsyRS8cmFNkr0LjCD8gr/07DI2zkarj3J6jwUsYqSybunZ1ybS4MERTvTQnGJv6lowD67ERXXPKkgNaZGD5dxYhPIMDCM6ZjTnki2BgfT2tzMh+cp4ThrTIXKKPwUTcQiKhLRu58tinpp1kpPh69k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719843477; c=relaxed/simple; bh=o7pgEsl1M4jkRAL2OMPP8br1xBPkYV2QP+YAJ1OanhY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b+TJPyqD5K4vYH4te8CO46UMdhwqmDEECtPw/P1KCIL0dfsyYNa+G+P7YzyorVsJ8cy9NHkJrEzb9BKozKTjE49ASo7A+b7c9l/slErTo+lYaY4jUuiW0/3xYWioO1mLBTULut9KaIAPBSja2XIjSM37a7cyYk9pJwDrh0w1k6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Y4y4tOHH; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Y4y4tOHH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719843476; x=1751379476; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=o7pgEsl1M4jkRAL2OMPP8br1xBPkYV2QP+YAJ1OanhY=; b=Y4y4tOHHwlx6Z4AB22771+XuUJrweW9EwSgCFPe02HjRWJHzuuidNsTF 7L/vOhPIjj2CzDQ2sKOuww6qu1abNbzvC8CZBXcVOhivD+2hRcQiHsnJF eCiWVz/zp6CDMbtZJDP7/omzCvbPEEqPLObmrvyf4zRraNrlz/6HOnZAa effupVhnqHIAp67mHcKIcB6C2G6ENAodSWz2HYEihgLwo0IVwrPfijr7T /qOo6UkpFw0y0dZy/7nr01IdMAAICtmGLRdoJ3r/tS1hx9dln7wv9NhuH ThygCE1nxx4QVYhqDUUkeCrmsAps1kTVB6GwkxxbfYfwZVdT+NqqR3lVz Q==; X-CSE-ConnectionGUID: cdt/laK2SZ62C1PR0bmMdw== X-CSE-MsgGUID: 573eu4eMQBi4tCQCAJDKYA== X-IronPort-AV: E=McAfee;i="6700,10204,11120"; a="27566477" X-IronPort-AV: E=Sophos;i="6.09,176,1716274800"; d="scan'208";a="27566477" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2024 07:17:52 -0700 X-CSE-ConnectionGUID: PfDVPbnoT7uDUals/09nMg== X-CSE-MsgGUID: GecbTaXQTQG3FQ/L7MH5nw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,176,1716274800"; d="scan'208";a="49880786" Received: from awvttdev-05.aw.intel.com ([10.228.212.156]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2024 07:17:51 -0700 From: "Michael J. Ruhl" To: intel-xe@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, david.e.box@linux.intel.com, ilpo.jarvinen@linux.intel.com, matthew.brost@intel.com Cc: michael.j.ruhl@intel.com Subject: [PATCH v5 5/6] platform/x86/intel/pmt: Add support for PMT base adjust Date: Mon, 1 Jul 2024 10:17:26 -0400 Message-ID: <20240701141730.3585133-6-michael.j.ruhl@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240701141730.3585133-1-michael.j.ruhl@intel.com> References: <20240701141730.3585133-1-michael.j.ruhl@intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 DVSEC offsets are based on the endpoint BAR. If an endpoint is not avialable allow the offset information to be adjusted by the parent driver. Signed-off-by: Michael J. Ruhl --- drivers/platform/x86/intel/pmt/class.h | 1 + drivers/platform/x86/intel/pmt/telemetry.c | 9 +++++++++ drivers/platform/x86/intel/vsec.c | 1 + include/linux/intel_vsec.h | 2 ++ 4 files changed, 13 insertions(+) diff --git a/drivers/platform/x86/intel/pmt/class.h b/drivers/platform/x86/intel/pmt/class.h index a267ac964423..984cd40ee814 100644 --- a/drivers/platform/x86/intel/pmt/class.h +++ b/drivers/platform/x86/intel/pmt/class.h @@ -46,6 +46,7 @@ struct intel_pmt_entry { void __iomem *base; struct pmt_callbacks *cb; unsigned long base_addr; + s32 base_adjust; size_t size; u32 guid; int devid; diff --git a/drivers/platform/x86/intel/pmt/telemetry.c b/drivers/platform/x86/intel/pmt/telemetry.c index c9feac859e57..5c44e500e8f6 100644 --- a/drivers/platform/x86/intel/pmt/telemetry.c +++ b/drivers/platform/x86/intel/pmt/telemetry.c @@ -78,6 +78,13 @@ static int pmt_telem_header_decode(struct intel_pmt_entry *entry, header->access_type = TELEM_ACCESS(readl(disc_table)); header->guid = readl(disc_table + TELEM_GUID_OFFSET); header->base_offset = readl(disc_table + TELEM_BASE_OFFSET); + if (entry->base_adjust) { + u32 new_base = header->base_offset + entry->base_adjust; + + dev_dbg(dev, "Adjusting baseoffset from 0x%x to 0x%x\n", + header->base_offset, new_base); + header->base_offset = new_base; + } /* Size is measured in DWORDS, but accessor returns bytes */ header->size = TELEM_SIZE(readl(disc_table)); @@ -302,6 +309,8 @@ static int pmt_telem_probe(struct auxiliary_device *auxdev, const struct auxilia for (i = 0; i < intel_vsec_dev->num_resources; i++) { struct intel_pmt_entry *entry = &priv->entry[priv->num_entries]; + entry->base_adjust = intel_vsec_dev->base_adjust; + mutex_lock(&ep_lock); ret = intel_pmt_dev_create(entry, &pmt_telem_ns, intel_vsec_dev, i); mutex_unlock(&ep_lock); diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c index 7b5cc9993974..be079d62a7bc 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -212,6 +212,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he intel_vsec_dev->num_resources = header->num_entries; intel_vsec_dev->quirks = info->quirks; intel_vsec_dev->base_addr = info->base_addr; + intel_vsec_dev->base_adjust = info->base_adjust; intel_vsec_dev->priv_data = info->priv_data; if (header->id == VSEC_ID_SDSI) diff --git a/include/linux/intel_vsec.h b/include/linux/intel_vsec.h index 003301783331..930eab246fa1 100644 --- a/include/linux/intel_vsec.h +++ b/include/linux/intel_vsec.h @@ -79,6 +79,7 @@ struct intel_vsec_platform_info { unsigned long caps; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; struct intel_vsec_device { @@ -92,6 +93,7 @@ struct intel_vsec_device { size_t priv_data_size; unsigned long quirks; u64 base_addr; + s32 base_adjust; }; int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent,