diff mbox series

[1/2] platform/x86/intel/pmc: Fix ioremap of bad address

Message ID 20241018030357.3580487-1-david.e.box@linux.intel.com (mailing list archive)
State Changes Requested, archived
Headers show
Series [1/2] platform/x86/intel/pmc: Fix ioremap of bad address | expand

Commit Message

David E. Box Oct. 18, 2024, 3:03 a.m. UTC
In pmc_core_ssram_get_pmc(), the physical addresses for hidden SSRAM
devices are retrieved from the MMIO region of the primary SSRAM device. If
additional devices are not present, the address returned is zero.
Currently, the code does not check for this condition, resulting in ioremap
incorrectly attempting to map address 0. Add a check for a zero address and
return 0 if no additional devices are found, as it is not an error for the
device to be absent.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Fixes: a01486dc4bb1 ("platform/x86/intel/pmc: Cleanup SSRAM discovery")
---
 drivers/platform/x86/intel/pmc/core_ssram.c | 4 ++++
 1 file changed, 4 insertions(+)


base-commit: 8e929cb546ee42c9a61d24fae60605e9e3192354
diff mbox series

Patch

diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c
index c259c96b7dfd..70e03bd53740 100644
--- a/drivers/platform/x86/intel/pmc/core_ssram.c
+++ b/drivers/platform/x86/intel/pmc/core_ssram.c
@@ -267,8 +267,12 @@  pmc_core_ssram_get_pmc(struct pmc_dev *pmcdev, int pmc_idx, u32 offset)
 		/*
 		 * The secondary PMC BARS (which are behind hidden PCI devices)
 		 * are read from fixed offsets in MMIO of the primary PMC BAR.
+		 * If a device is not present, the value will be 0.
 		 */
 		ssram_base = get_base(tmp_ssram, offset);
+		if (!ssram_base)
+			return 0;
+
 		ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);
 		if (!ssram)
 			return -ENOMEM;