diff mbox series

[v2,2/2] platform/x86/amd: amd_3d_vcache: Add sysfs ABI documentation

Message ID 20241021134654.337368-3-Basavaraj.Natikar@amd.com (mailing list archive)
State Changes Requested, archived
Headers show
Series Add support of AMD 3D V-Cache optimizer driver | expand

Commit Message

Basavaraj Natikar Oct. 21, 2024, 1:46 p.m. UTC
Add documentation for the amd_3d_vcache sysfs bus platform driver
interface so that userspace applications can use it to change mode
preferences, either frequency or cache.

Co-developed-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
---
 .../sysfs-bus-platform-drivers-amd_x3d_vcache        | 12 ++++++++++++
 MAINTAINERS                                          |  1 +
 2 files changed, 13 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache

Comments

Armin Wolf Oct. 21, 2024, 2:11 p.m. UTC | #1
Am 21.10.24 um 15:46 schrieb Basavaraj Natikar:

> Add documentation for the amd_3d_vcache sysfs bus platform driver
> interface so that userspace applications can use it to change mode
> preferences, either frequency or cache.

Reviewed-by: Armin Wolf <W_Armin@gmx.de>

>
> Co-developed-by: Perry Yuan <perry.yuan@amd.com>
> Signed-off-by: Perry Yuan <perry.yuan@amd.com>
> Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
> Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
> ---
>   .../sysfs-bus-platform-drivers-amd_x3d_vcache        | 12 ++++++++++++
>   MAINTAINERS                                          |  1 +
>   2 files changed, 13 insertions(+)
>   create mode 100644 Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
> new file mode 100644
> index 000000000000..5ff1f1a8c9b6
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
> @@ -0,0 +1,12 @@
> +What:		/sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode
> +Date:           October 2024
> +KernelVersion:	6.13
> +Contact:	Basavaraj Natikar <Basavaraj.Natikar@amd.com>
> +Description:	(RW) AMD 3D V-Cache optimizer allows users to switch CPU core
> +		rankings dynamically.
> +
> +		This file switches between these two modes:
> +		- "frequency" cores within the faster CCD are prioritized before
> +		those in the slower CCD.
> +		- "cache" cores within the larger L3 CCD are prioritized before
> +		those in the smaller L3 CCD.
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 11b829956499..ca9c666caf7f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -970,6 +970,7 @@ M:	Basavaraj Natikar <Basavaraj.Natikar@amd.com>
>   R:	Mario Limonciello <mario.limonciello@amd.com>
>   L:	platform-driver-x86@vger.kernel.org
>   S:	Supported
> +F:	Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
>   F:	drivers/platform/x86/amd/x3d_vcache.c
>
>   AMD ADDRESS TRANSLATION LIBRARY (ATL)
diff mbox series

Patch

diff --git a/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
new file mode 100644
index 000000000000..5ff1f1a8c9b6
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
@@ -0,0 +1,12 @@ 
+What:		/sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode
+Date:           October 2024
+KernelVersion:	6.13
+Contact:	Basavaraj Natikar <Basavaraj.Natikar@amd.com>
+Description:	(RW) AMD 3D V-Cache optimizer allows users to switch CPU core
+		rankings dynamically.
+
+		This file switches between these two modes:
+		- "frequency" cores within the faster CCD are prioritized before
+		those in the slower CCD.
+		- "cache" cores within the larger L3 CCD are prioritized before
+		those in the smaller L3 CCD.
diff --git a/MAINTAINERS b/MAINTAINERS
index 11b829956499..ca9c666caf7f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -970,6 +970,7 @@  M:	Basavaraj Natikar <Basavaraj.Natikar@amd.com>
 R:	Mario Limonciello <mario.limonciello@amd.com>
 L:	platform-driver-x86@vger.kernel.org
 S:	Supported
+F:	Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache
 F:	drivers/platform/x86/amd/x3d_vcache.c
 
 AMD ADDRESS TRANSLATION LIBRARY (ATL)