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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 09:19:54.7160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a2512b1-c1af-403d-8abd-08dd4a7d3f34 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7014 Add new field 'capability_mask' to structs 'mlxreg_core_data' and 'mlxreg_core_item'. The ‘capabilty_mask’ is associated with the relevant capability registers, indicating which attributes should be handled and which ignored. Register contains bitmask of attributes or number of attributtes, which should be handled. While 'capability mask' is superset. Reviewed-by: Felix Radensky Signed-off-by: Vadim Pasternak --- v5->v6 Revised after comments pointed out by Ilpo: - Drop 'capability_bit' from structure 'mlxreg_core_data', since it is not used. --- include/linux/platform_data/mlxreg.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h index 0b9f81a6f753..b2a3377a28e5 100644 --- a/include/linux/platform_data/mlxreg.h +++ b/include/linux/platform_data/mlxreg.h @@ -118,6 +118,7 @@ struct mlxreg_hotplug_device { * @mask: attribute access mask; * @bit: attribute effective bit; * @capability: attribute capability register; + * @capability_mask: superset mask for capability register; * @reg_prsnt: attribute presence register; * @reg_sync: attribute synch register; * @reg_pwr: attribute power register; @@ -138,6 +139,7 @@ struct mlxreg_core_data { u32 mask; u32 bit; u32 capability; + u32 capability_mask; u32 reg_prsnt; u32 reg_sync; u32 reg_pwr; @@ -162,6 +164,7 @@ struct mlxreg_core_data { * @reg: group interrupt status register; * @mask: group interrupt mask; * @capability: group capability register; + * @capability_mask: superset mask for capability register; * @cache: last status value for elements fro the same group; * @count: number of available elements in the group; * @ind: element's index inside the group; @@ -175,6 +178,7 @@ struct mlxreg_core_item { u32 reg; u32 mask; u32 capability; + u32 capability_mask; u32 cache; u8 count; u8 ind;