From patchwork Thu Feb 27 12:15:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Choong Yong Liang X-Patchwork-Id: 13994345 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1DD122E00E; Thu, 27 Feb 2025 12:17:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740658654; cv=none; b=E3FxvxHKnZ9aZXtAPSr9Hq63aM2zvfz0qwjg+jfpcYti4rvJ7QvA11qgh/D4h4+ku7OzPxK7GH0vaVMPZZ+ZG4QtqyYGn5oai9ZJwuuJ+D3DwFA3o8E4vrpad3h8Xh0sBalxq1RCj4lOJFmUiCkOG4iIG6AzKsRSVK49f3pTSnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740658654; c=relaxed/simple; bh=cmKtuwnc2KIDaRI+wvWtnzBRpft8byHlKWXn0enjH2M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NS20ZM8J5mZ1iZVNzWkSM9WOQbTW+Oi8Rl+UWaNbr6XSzVc15h0Mgq/V+H47WMqKi7PxZRW3Xo9HVkhU6Ewt1cU7uGG0aG86nZNCLC0+EsUznKN8usS/+bMH40fRI5naN2efbGDVEFjZNtM4nrwZnMhgXCOM7m58JGcqx6HuPpU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hDS+IVK9; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hDS+IVK9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740658653; x=1772194653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cmKtuwnc2KIDaRI+wvWtnzBRpft8byHlKWXn0enjH2M=; b=hDS+IVK9jV3/+TOd28JIlk+9oM1Ta8ZJHojzv7DIfqiF/NZGTSjcoFDq FqE1xt6grf6qmkEGJ1gXGrisXuZ2GD2qoQ04in5bORrB77MXdIbZOp5bk ffI0+5nZu7MJKqJQi33/RPPS1fwmbliff8OxUKblwdUIHzeqI0Z6nxy4A M0xCsARDiuJxfYDjctq45QBPHl8vAXxgyulwDJ7/oS86XE9AnJsJ062XP APBpJ729DIUyXftZFF7Ft8RN6TAgIvditWRmwEVYXTw7PCs2k3lvIkoXb hwhe2j/IKQyrqnDB6R5fkLHdw6oKz82uzV44GME2IADtcmsJiv7wTLtEI A==; X-CSE-ConnectionGUID: CPxCdRpTT02VPv6v+jyPMw== X-CSE-MsgGUID: F6lOC1kxR9aYFI5lAkYizA== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="41464441" X-IronPort-AV: E=Sophos;i="6.13,319,1732608000"; d="scan'208";a="41464441" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2025 04:17:32 -0800 X-CSE-ConnectionGUID: 7vofMf2LTX++1OfF11Gvog== X-CSE-MsgGUID: r3sYWK5QQbiJ+y4gBWx37A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="117519408" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.227.39]) by orviesa007.jf.intel.com with ESMTP; 27 Feb 2025 04:17:25 -0800 From: Choong Yong Liang To: Simon Horman , Jose Abreu , Jose Abreu , David E Box , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H . Peter Anvin" , Rajneesh Bhardwaj , David E Box , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Jiawen Wu , Mengyuan Lou , Heiner Kallweit , Russell King , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Richard Cochran , Serge Semin Cc: x86@kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v9 6/6] net: stmmac: interface switching support for ADL-N platform Date: Thu, 27 Feb 2025 20:15:22 +0800 Message-Id: <20250227121522.1802832-7-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250227121522.1802832-1-yong.liang.choong@linux.intel.com> References: <20250227121522.1802832-1-yong.liang.choong@linux.intel.com> Precedence: bulk X-Mailing-List: platform-driver-x86@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The intel_config_serdes function was provided to handle interface mode changes for the ADL-N platform. The Modphy register lane was provided to configure the serdes when changing interface modes. Signed-off-by: Michael Sit Wei Hong Signed-off-by: Choong Yong Liang --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index f73a48f98581..9c8de47ee149 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -87,6 +87,7 @@ static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = { }; static const int ehl_tsn_lane_regs[] = {7, 8, 9, 10, 11}; +static const int adln_tsn_lane_regs[] = {6}; static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, const struct dmi_system_id *dmi_list) @@ -1004,6 +1005,55 @@ static int adls_sgmii_phy1_data(struct pci_dev *pdev, static struct stmmac_pci_info adls_sgmii1g_phy1_info = { .setup = adls_sgmii_phy1_data, }; + +static int adln_common_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + struct intel_priv_data *intel_priv = plat->bsp_priv; + + plat->rx_queues_to_use = 6; + plat->tx_queues_to_use = 4; + plat->clk_ptp_rate = 204800000; + + plat->safety_feat_cfg->tsoee = 1; + plat->safety_feat_cfg->mrxpee = 0; + plat->safety_feat_cfg->mestee = 1; + plat->safety_feat_cfg->mrxee = 1; + plat->safety_feat_cfg->mtxee = 1; + plat->safety_feat_cfg->epsi = 0; + plat->safety_feat_cfg->edpp = 0; + plat->safety_feat_cfg->prtyen = 0; + plat->safety_feat_cfg->tmouten = 0; + + intel_priv->tsn_lane_regs = adln_tsn_lane_regs; + intel_priv->max_tsn_lane_regs = ARRAY_SIZE(adln_tsn_lane_regs); + + return intel_mgbe_common_data(pdev, plat); +} + +static int adln_sgmii_phy0_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + struct intel_priv_data *intel_priv = plat->bsp_priv; + + plat->bus_id = 1; + plat->phy_interface = PHY_INTERFACE_MODE_SGMII; + plat->serdes_powerup = intel_serdes_powerup; + plat->serdes_powerdown = intel_serdes_powerdown; + plat->mac_finish = intel_mac_finish; + + intel_priv->pid_1g.regs = pid_modphy1_1g_regs; + intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); + intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; + intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); + + return adln_common_data(pdev, plat); +} + +static struct stmmac_pci_info adln_sgmii1g_phy0_info = { + .setup = adln_sgmii_phy0_data, +}; + static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { { .func = 6, @@ -1386,7 +1436,7 @@ static const struct pci_device_id intel_eth_pci_id_table[] = { { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) }, - { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) }, + { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &adln_sgmii1g_phy0_info) }, { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) }, {} };