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Fri, 14 Feb 2020 05:21:05 -0800 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01EDL5i3013702; Fri, 14 Feb 2020 05:21:05 -0800 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1j2au0-0006fP-PX; Fri, 14 Feb 2020 05:21:05 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 4FBD513C0374; Fri, 14 Feb 2020 18:46:58 +0530 (IST) From: Sai Pavan Boddu To: "Edgar E . Iglesias" , Alistair Francis , Peter Maydell , Anthony Liguori , afaerber@suse.de Subject: [PATCH 0/3] Fix number of priority bits in zynq gic Date: Fri, 14 Feb 2020 18:46:49 +0530 Message-Id: <1581686212-9625-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(136003)(39850400004)(396003)(376002)(199004)(189003)(426003)(4326008)(70586007)(8936002)(356004)(81156014)(8676002)(6666004)(316002)(42186006)(336012)(70206006)(2616005)(5660300002)(110136005)(6266002)(81166006)(186003)(478600001)(4744005)(2906002)(26005)(36756003); DIR:OUT; SFP:1101; SCL:1; SRVR:SN1PR02MB3904; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; A:1; MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 847add65-cdc5-4a4d-7df5-08d7b150c298 X-MS-TrafficTypeDiagnostic: SN1PR02MB3904: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-Forefront-PRVS: 03137AC81E X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 49Qg4fF1s3yDnW97n15YDi8Cb5fCh47hRXMzOHPfz67yuEfvCoVtnMM95FMiUJJGmcXRW5PWV+aJsOFU+FW7REg4G/Cyr456O3K1R4X/qPt4iciq1fML3L4tx607dBlQ/PInESuvIU65hzAbD4fkMStCmSYKIhCPgD/CGnGFNgdzkBCaP79soDadtcg2CDBTt511xHMB4UrAbRjyigPf0wiJ7gQ3ImUO0fnA+tW5sC0w016FYQpkD/StlPnSXnk0QU3supuNU96+5wbWv4cxanqXr7a7oORH+MblKCEZFiZa1qlPrz9LL9QsQTMBwckT5XS8H+mAoR1lVXcv8Ji7G7daaEK+8lQ4gQDLfns/e1k/HYvJHF36y6ZMQJ2rsE5RBB0POUTJnYEbHxQgaaYXX4wHO96vDvkAgSJ9D04N3FB7BVVlpUxl9vyL21U08YeW X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 13:21:11.5367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 847add65-cdc5-4a4d-7df5-08d7b150c298 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR02MB3904 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.94.55 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This patch series implements the mask for un-implemented priority bits in arm-gic. Which will return the expected number of priority bits on read. Sai Pavan Boddu (3): arm_gic: Mask the un-supported priority bits cpu/a9mpcore: Add num priority bits property arm/xilinx_zynq: Set number of priority bits hw/arm/xilinx_zynq.c | 1 + hw/cpu/a9mpcore.c | 2 ++ hw/intc/arm_gic.c | 9 ++++++--- hw/intc/arm_gic_common.c | 1 + include/hw/cpu/a9mpcore.h | 1 + include/hw/intc/arm_gic_common.h | 1 + 6 files changed, 12 insertions(+), 3 deletions(-)