Message ID | 1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com (mailing list archive) |
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Mon, 24 Feb 2020 01:44:09 -0800 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 01O9i8Qt029113; Mon, 24 Feb 2020 01:44:08 -0800 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from <saipava@xhdsaipava40.xilinx.com>) id 1j6AHX-0008PF-S7; Mon, 24 Feb 2020 01:44:08 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 774E813C0374; Mon, 24 Feb 2020 15:09:35 +0530 (IST) From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> To: "Edgar E . Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Peter Maydell <peter.maydell@linaro.org>, Anthony Liguori <anthony@codemonkey.ws>, afaerber@suse.de Subject: [PATCH v3 0/3] Fix number of priority bits for arm boards Date: Mon, 24 Feb 2020 15:09:21 +0530 Message-Id: <1582537164-764-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(136003)(346002)(39860400002)(396003)(376002)(189003)(199004)(336012)(81166006)(186003)(42186006)(5660300002)(426003)(2906002)(8676002)(8936002)(316002)(81156014)(4326008)(110136005)(26005)(356004)(478600001)(6266002)(70586007)(70206006)(2616005)(6666004)(36756003)(4744005); DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR02MB3392; H:xsj-pvapsmtpgw01; FPR:; SPF:Pass; LANG:en; PTR:unknown-60-83.xilinx.com; MX:1; A:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b7dbeba8-f025-49e0-b0ba-08d7b90e1c1c X-MS-TrafficTypeDiagnostic: MWHPR02MB3392: X-Microsoft-Antispam-PRVS: <MWHPR02MB3392B8B07AB5E0309DED7238CAEC0@MWHPR02MB3392.namprd02.prod.outlook.com> X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 032334F434 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aVangZooHEYKRvFmRQIeOUe94Ocol2G5ScVFfrtiCP6UhkP5EcasiXD7rNyoz+5XRw/nSwJ6sAwTe3pFd8sQL/HW9J40WHkpDhGBNX/5XaTYUxKYeFtyds2/8+2xgDKR5zRCHiXjIt+Fbmw52WWRf9+2wY3N/cpWEgetejfzkdhcKQz0BEt++eGxmIilm3W82PoxHZX5+3i7Pf0o7uk/xTRSUJFgEFmtPq79cdnvyT+qKvShQmJdM9dXd2oUqIdx3TEzC6MF2VVwetGMclakIiLlijs6ENMFIWbbHu/0Y6CSCIebvbNWUc7WrDaGNp3zVF6FCTAgzzeRRLMkARWPfcIGh4wDWZg1+C6ErzXaklDWu8DGuPhNHc4BI/mudBEVOStVBmjhzfmUQIlwotfgDslO5l2uLW5vqy06ndUbxKTUKWAaPe5WgNfekKmGtf4j X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2020 09:44:14.6796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7dbeba8-f025-49e0-b0ba-08d7b90e1c1c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB3392 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 40.107.243.62 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> |
Series |
Fix number of priority bits for arm boards
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expand
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On Mon, 24 Feb 2020 at 09:44, Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> wrote: > > This patch series implements the mask for unimplemented priority bits in > arm-gic. Which will return the expected number of priority bits on read. > > Changes for V2: > Followed gicv3 code for defining mask for unimplemented bits > Hardcoded num priority bits for A9 and ARM11MPCore boards > Changes for V3: > Fixed the code as suggested in V1. > Implemented checks for max and min priority bits. > > Sai Pavan Boddu (3): > arm_gic: Mask the un-supported priority bits > cpu/a9mpcore: Set number of GIC priority bits to 5 > cpu/arm11mpcore: Set number of GIC priority bits to 4 Applied to target-arm.next, thanks. (I tweaked a few of the commit messages to give a little more detail.) -- PMM