From patchwork Sat Oct 20 07:14:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastian Koppelmann X-Patchwork-Id: 10650283 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 741A9112B for ; Sat, 20 Oct 2018 07:20:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C8F52858F for ; Sat, 20 Oct 2018 07:20:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50A0D2859A; Sat, 20 Oct 2018 07:20:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 096842858F for ; Sat, 20 Oct 2018 07:20:18 +0000 (UTC) Received: from localhost ([::1]:53979 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlYO-0006Jh-9g for patchwork-qemu-devel@patchwork.kernel.org; Sat, 20 Oct 2018 03:20:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40764) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDlTV-00021S-J8 for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDlTQ-0004CI-Ga for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:05 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:36814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDlTQ-0004Az-3G for qemu-devel@nongnu.org; Sat, 20 Oct 2018 03:15:00 -0400 Received: from magmaria.uni-paderborn.de ([131.234.189.24] helo=localhost.localdomain) by mail.uni-paderborn.de with esmtp (Exim 4.89 zuban) id 1gDlTN-0005A9-Jl; Sat, 20 Oct 2018 09:14:57 +0200 Received: from mail.uni-paderborn.de by magmaria with queue id 2939441-3; Sat, 20 Oct 2018 07:14:57 GMT X-Envelope-From: Received: from aftr-95-222-26-83.unity-media.net ([95.222.26.83] helo=schnipp.lan) by mail.uni-paderborn.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89 telepax) id 1gDlTM-0008Eu-5i; Sat, 20 Oct 2018 09:14:56 +0200 From: Bastian Koppelmann To: mjc@sifive.com, sagark@eecs.berkeley.edu, palmer@sifive.com, kbastian@mail.uni-paderborn.de Date: Sat, 20 Oct 2018 09:14:22 +0200 Message-Id: <20181020071451.27808-1-kbastian@mail.uni-paderborn.de> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-PMX-Version: 6.4.5.2775670, Antispam-Engine: 2.7.2.2107409, Antispam-Data: 2018.10.20.70916, AntiVirus-Engine: 5.53.0, AntiVirus-Data: 2018.10.10.5530001 X-IMT-Spam-Score: 0.0 () X-IMT-Authenticated-Sender: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 131.234.142.9 Subject: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Hi, this patchset converts the RISC-V decoder to decodetree in three major steps: 1) Convert 32-bit instructions to decodetree [Patch 1-14]: Many of the gen_* functions are called by the decode functions for 16-bit and 32-bit functions. If we move translation code from the gen_* functions to the generated trans_* functions of decode-tree, we get a lot of duplication. Therefore, we mostly generate calls to the old gen_* function which are properly replaced after step 2). Each of the trans_ functions are grouped into files corresponding to their ISA extension, e.g. addi which is in RV32I is translated in the file 'trans_rvi.inc.c'. 2) Convert 16-bit instructions to decodetree [Patch 15-17]: All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus, we convert the arguments in the 16 bit trans_ function to the arguments of the corresponding 32 bit instruction and call the 32 bit trans_ function. 3) Remove old manual decoding in gen_* function [Patch 17-28]: this move all manual translation code into the trans_* instructions of decode tree, such that we can remove the old decode_* functions. the full tree can be found here: https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2 Cheers, Bastian v1->v2: - ex_shift_amount returns uint32_t - use ctx->env instead of current_cpu->env_ptr - fixed functionspacing - RISCV32 now returns false instead of raising an exception - shift translators now also use gen_arithm_imm() - simplified fence/fence_i as suggested by Richard - simplified gen_amo() with function pointers - rs2 @atom_ld is now decimal - use simplfied gen_amo() with function pointers - REQUIRE_FPU uses do {} while (0) - Add REQUIRE_FPU to arithm helpers - RISCV32 now returns false instead of raising an exception - Add REQUIRE_FPU to arithm helpers - Stack allocate arg_c_* structs - ex_rvc_register returns int - special case of trans_c_addi4spn() returns false - consistently return false for reserved cases instead of raising an exception - simplified trans_c_srli by Richard's suggestion - remove extract_cj() since its result isn't used - trans_branch -> gen_branch - trans_load -> gen_load - removed negative memop check - trans_store -> gen_store - removed negative memop check - trans_arith_imm -> gen_arith_imm - Add missing TARGET_RISC64 checks - Reimplement shift translators that were omited in [0004/0028] - trans_shift -> gen_shift - Add missing TARGET_RISCV64 conditions - trans_arith_w -> gen_arith_w - Add missing gen_exception_illegal - dropped 0028 Bastian Koppelmann (29): target/riscv: Move CPURISCVState pointer to DisasContext targer/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RVXI load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv: Rename trans_arith to gen_arith target/riscv/Makefile.objs | 17 + target/riscv/insn16.decode | 126 ++ target/riscv/insn32.decode | 256 +++ .../riscv/insn_trans/trans_privileged.inc.c | 111 ++ target/riscv/insn_trans/trans_rva.inc.c | 244 +++ target/riscv/insn_trans/trans_rvc.inc.c | 337 ++++ target/riscv/insn_trans/trans_rvd.inc.c | 413 ++++ target/riscv/insn_trans/trans_rvf.inc.c | 402 ++++ target/riscv/insn_trans/trans_rvi.inc.c | 629 ++++++ target/riscv/insn_trans/trans_rvm.inc.c | 125 ++ target/riscv/translate.c | 1756 ++--------------- 11 files changed, 2853 insertions(+), 1563 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c --- 2.19.1