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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4379; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Q1AmSIBKtMxxbx4qiZ8kDChk1TULGO3A9fsfczyHYFwtoH4loGM48oPea1xRNv+69nVml+URr7d/NIZR88WERMeyONj7ITk8hdXRfAH/u+vYV/AE6RAMxjtfwPGdk2eiLka+8iJ1GJA9aFfk21IEJeilZoCyitFvZoQXxk3ycD6F7ydsiynZcCAaHaOYHSkrEMmff5xmgorn71arWI7oGlDkRj+07Z+D666LzWMKCcF/R8g+WcLWC6WUvMxocU7arCv0kGOH556OkcyyUghtTPblcDapTIhcVwWUKW7G3qKW3gUn2GgYGkawJhB3ehJU spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4fd6b66f-94c3-4208-80fb-08d65f7c2013 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Dec 2018 15:20:04.1361 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4379 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.71.107 Subject: [Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The ARM PMU implementation currently contains a basic cycle counter, but it is often useful to gather counts of other events, filter them based on execution mode, and/or be notified on counter overflow. These patches flesh out the implementations of various PMU registers including PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent arbitrary counter types, implement mode filtering, send interrupts on counter overflow, and add instruction, cycle, and software increment events. Since v9 [1] I have made the following changes: * Added a clarifying comment about how the PMU timer's migration is handled * Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon == 0xf * Added TRACEFILT to the ID_DFR0 field definitions [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html Aaron Lindsay (14): migration: Add post_save function to VMStateDescription target/arm: Reorganize PMCCNTR accesses target/arm: Swap PMU values before/after migrations target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR target/arm: Implement PMOVSSET target/arm: Define FIELDs for ID_DFR0 target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER target/arm: PMU: Add instruction and cycle events target/arm: PMU: Set PMCR.N to 4 target/arm: Implement PMSWINC target/arm: Send interrupts on PMU counter overflow docs/devel/migration.rst | 9 +- include/migration/vmstate.h | 1 + migration/vmstate.c | 13 +- target/arm/cpu.c | 28 +- target/arm/cpu.h | 81 +++- target/arm/cpu64.c | 4 - target/arm/helper.c | 808 ++++++++++++++++++++++++++++++++---- target/arm/machine.c | 24 ++ 8 files changed, 863 insertions(+), 105 deletions(-)