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DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB2550; H:DM5PR12MB2471.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: FSA7Q8FeetkQsmuwCSxu2mGD4qm+j0S/VJlOZPkh6hbb3+28nXa8NMzaZZztzYrf1a3jCpWNFDF19ndGYYZreNEc0eD9fl0IRR0/WZezU7VXnbJqI+oxFYHyhl7VssEOdomczQss0RKo5kK1Ad06P3NDHsrX3NxiCI9c4dNHdyEn3Yfj8H+kdn+QS51qpI7GqollwMjc4DdWFdiA17KtiS7bd5DbPI36jbgr6MxE2LngkThmKWE9uURxchs4Dy0hTb3ydPbka1jOffqTPD59/pYxN2PskCOHRYJFauXCcPzduqq6TvrLfUXxLJx+Om1555biNGxjiNyCdRnjSi0emRwJEiCjxrxi+6Texe/JVAKQHWukGBlmYOozC8U4sv5vV07bAx2SO+JSO16TCp3xyOf6XqTqMpG4n9rbKAyCrQ0= Content-ID: <2598662BDF007D46826237B9003B6D08@namprd12.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f332b9ea-bdf7-478a-c2c8-08d7160db6f2 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Jul 2019 23:20:45.8591 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: bmoger@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2550 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.76.58 Subject: [Qemu-devel] [RFC PATCH 0/5] APIC ID fixes for AMD EPYC CPU models X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Moger, Babu" , "qemu-devel@nongnu.org" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP These series fixes the problems encoding APIC ID for AMD EPYC cpu models. https://bugzilla.redhat.com/show_bug.cgi?id=1728166 This is the first pass to give an idea of the changes required to address the issue. Please feel free to comment. Currently, apic id is decoded based on sockets/dies/cores/threads. This appears to work for most standard configurations for AMD and other vendors. But this decoding does not follow AMD's APIC ID enumeration. In some cases this causes CPU topology inconstancy. While booting guest Kernel is trying to validate topology. It finds the topology not aligning to EPYC models. To fix the problem we need to build the topology as per the Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. It is available at https://www.amd.com/en/support/tech-docs Here is the text from the PPR. 2.1.10.2.1.3 ApicId Enumeration Requirements Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdCoreIdSize], the number of least significant bits in the Initial APIC ID that indicate core ID within a processor, in constructing per-core CPUID masks. Core::X86::Cpuid::SizeId[ApicIdCoreIdSize] determines the maximum number of cores (MNC) that the processor could theoretically support, not the actual number of cores that are actually implemented or enabled on the processor, as indicated by Core::X86::Cpuid::SizeId[NC]. Each Core::X86::Apic::ApicId[ApicId] register is preset as follows: • ApicId[6] = Socket ID. • ApicId[5:4] = Node ID. • ApicId[3] = Logical CCX L3 complex ID • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,LogicalCoreID[1:0]}. """ Babu Moger (5): hw/boards: Add sockets in CpuTopology structure hw/i386: Add AMD EPYC topology encoding i386: Use topology functions from topology.h hw/i386: Generate apicid based on cpu_type i386: Fix pkg_id offset EPYC hw/core/machine.c | 1 + hw/i386/pc.c | 82 ++++++++++++++++--- include/hw/boards.h | 2 + include/hw/i386/topology.h | 140 ++++++++++++++++++++++++++++++++ target/i386/cpu.c | 160 +++++++++---------------------------- vl.c | 1 + 6 files changed, 251 insertions(+), 135 deletions(-)