Message ID | 20191128161718.24361-1-maz@kernel.org (mailing list archive) |
---|---|
Headers | show |
Series | target/arm: More HCR_EL2.TIDx fixes | expand |
On 2019-11-28 16:30, Peter Maydell wrote: > On Thu, 28 Nov 2019 at 16:17, Marc Zyngier <maz@kernel.org> wrote: >> >> I started looking the rest of the missing TIDx handling, >> and this resulted in the following patches. >> >> There is still one thing I'm a bit puzzled by though: >> >> HCR_EL2.TID0 mandates trapping of the AArch32 JIDR >> register, but I couldn't find a trace of it in the QEMU >> code, and trying to read it seems to generate an exception. >> >> It isn't like anyone is going to miss it, but I wonder if >> it should be implemented... It could also be that I'm missing >> the obvious and that my testing is broken! ;-) > > Hmm, I was under the impression that we correctly implemented > 'trivial Jazelle', but we obviously missed some of it > (we do have the handling of BXJ insns). > We should, yes, ideally, have RAZ/WI implementations > of JIDR, JMCR and JOSCR. OK, I'll have a look at this, and plumb the handling of TID0 in JIDR. > We also I think don't get right the fiddly detail about > attempting an exception return with SPSR.J set, but that's > not worth messing about with IMHO. Indeed. The less we hear about Jazelle, the better... ;-) Thanks, M.