mbox series

[v2,0/5] target/arm: More EL2 trapping fixes

Message ID 20191201122018.25808-1-maz@kernel.org (mailing list archive)
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Series target/arm: More EL2 trapping fixes | expand

Message

Marc Zyngier Dec. 1, 2019, 12:20 p.m. UTC 
Hi all,

This series is a follow-up on [1], which tried to address the
remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed the
comments that Peter and Edgar raised.

I've also tried to tackle missing traps generated by HSTR_EL2, which
got completely ignored so far. Note that this results in the use of a
new TB bit, which I understand is a rare resource. I'd welcome
comments on how to handle it differently if at all possible.

Finally, and as a bonus non-feature, I've added support for the
missing Jazelle registers, giving me the opportunity to allow trapping
of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)

I'm now going back to kernel stuff. I swear!

[1] https://patchew.org/QEMU/20191128161718.24361-1-maz@kernel.org/

Marc Zyngier (5):
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Add support for missing Jazelle system registers

 target/arm/cpu.h               |   2 +
 target/arm/helper-a64.h        |   2 +
 target/arm/helper.c            | 100 ++++++++++++++++++++++++++++++---
 target/arm/op_helper.c         |  21 +++++++
 target/arm/translate-vfp.inc.c |  18 +++++-
 target/arm/translate.c         |   3 +-
 target/arm/translate.h         |   2 +
 target/arm/vfp_helper.c        |  29 ++++++++++
 8 files changed, 165 insertions(+), 12 deletions(-)

Comments

Peter Maydell Dec. 6, 2019, 2:13 p.m. UTC | #1 
On Sun, 1 Dec 2019 at 12:20, Marc Zyngier <maz@kernel.org> wrote:
>
> Hi all,
>
> This series is a follow-up on [1], which tried to address the
> remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed the
> comments that Peter and Edgar raised.
>
> I've also tried to tackle missing traps generated by HSTR_EL2, which
> got completely ignored so far. Note that this results in the use of a
> new TB bit, which I understand is a rare resource. I'd welcome
> comments on how to handle it differently if at all possible.
>
> Finally, and as a bonus non-feature, I've added support for the
> missing Jazelle registers, giving me the opportunity to allow trapping
> of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)
>
> I'm now going back to kernel stuff. I swear!

To save you from having to roll a v3, I've fixed up the
handful of nits Richard and I found as I applied this
series to target-arm.next.

thanks
-- PMM
Marc Zyngier Dec. 6, 2019, 2:19 p.m. UTC | #2 
On 2019-12-06 14:13, Peter Maydell wrote:
> On Sun, 1 Dec 2019 at 12:20, Marc Zyngier <maz@kernel.org> wrote:
>>
>> Hi all,
>>
>> This series is a follow-up on [1], which tried to address the
>> remaining missing HCR_EL2.TIDx traps. I've hopefully now adressed 
>> the
>> comments that Peter and Edgar raised.
>>
>> I've also tried to tackle missing traps generated by HSTR_EL2, which
>> got completely ignored so far. Note that this results in the use of 
>> a
>> new TB bit, which I understand is a rare resource. I'd welcome
>> comments on how to handle it differently if at all possible.
>>
>> Finally, and as a bonus non-feature, I've added support for the
>> missing Jazelle registers, giving me the opportunity to allow 
>> trapping
>> of JIDR to EL2 using HCR_EL2.TID0. Yay, Christmas! ;-)
>>
>> I'm now going back to kernel stuff. I swear!
>
> To save you from having to roll a v3, I've fixed up the
> handful of nits Richard and I found as I applied this
> series to target-arm.next.

Ah, brilliant. Thanks a lot Peter.

         M.