| Message ID | 20191202063233.28523-1-tao3.xu@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add extra information to versioned CPU models | expand |
On 12/2/2019 2:32 PM, Tao Xu wrote: > This series of patches will remove MPX from Denverton, remove Remove > monitor from some CPU models. Add additional information for -cpu help > to indicate the changes in this version of CPU model. > > The output is as follows: > x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\[" > x86 Broadwell-v2 Intel Core Processor (Broadwell) [no TSX] > x86 Broadwell-v3 Intel Core Processor (Broadwell) [IBRS] > x86 Broadwell-v4 Intel Core Processor (Broadwell) [no TSX, IBRS] Above the changes of each Broadwell-v{2,3,4} are based on Broadwell-v1. > x86 Cascadelake-Server-v2 Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES] > x86 Cascadelake-Server-v3 Intel Xeon Processor (Cascadelake) [no TSX] But in the code, Cascadelake-Server-v3 inherits all the features in Cascadelake-Server-v2 and removes TSX related hle & rtm. So if we keep the same rule based on v1, it should be x86 Cascadelake-Server-v3 Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES, no TSX] > x86 Denverton-v2 Intel Atom Processor (Denverton) [no MPX, no MONITOR] > x86 Dhyana-v2 Hygon Dhyana Processor [no MONITOR] > x86 EPYC-v2 AMD EPYC Processor [IBPB] > x86 EPYC-v3 AMD EPYC Processor [IBPB, no MONITOR] > x86 Haswell-v2 Intel Core Processor (Haswell) [no TSX] > x86 Haswell-v3 Intel Core Processor (Haswell) [IBRS] > x86 Haswell-v4 Intel Core Processor (Haswell) [no TSX, IBRS] > x86 Icelake-Client-v2 Intel Core Processor (Icelake) [no TSX] > x86 Icelake-Server-v2 Intel Xeon Processor (Icelake) [no TSX] > x86 IvyBridge-v2 Intel Xeon E3-12xx v2 (Ivy Bridge) [IBRS] > x86 Nehalem-v2 Intel Core i7 9xx (Nehalem Class Core i7) [IBRS] > x86 Opteron_G3-v2 AMD Opteron 23xx (Gen 3 Class Opteron) [no MONITOR] > x86 SandyBridge-v2 Intel Xeon E312xx (Sandy Bridge) [IBRS] > x86 Skylake-Client-v2 Intel Core Processor (Skylake) [IBRS] > x86 Skylake-Client-v3 Intel Core Processor (Skylake) [no TSX, IBRS] > x86 Skylake-Server-v2 Intel Xeon Processor (Skylake) [IBRS] > x86 Skylake-Server-v3 Intel Xeon Processor (Skylake) [no TSX, IBRS] > x86 Snowridge-v2 Intel Atom Processor (SnowRidge) [no MPX] > x86 Snowridge-v3 Intel Atom Processor (SnowRidge) [no MPX, no MONITOR] > x86 Westmere-v2 Westmere E56xx/L56xx/X56xx (Nehalem-C) [IBRS] > > Tao Xu (4): > target/i386: Add Denverton-v2 (no MPX) CPU model > target/i386: Remove monitor from some CPU models > target/i386: Add new property note to versioned CPU models > target/i386: Add notes for versioned CPU models > > target/i386/cpu.c | 112 +++++++++++++++++++++++++++++++++++----------- > 1 file changed, 85 insertions(+), 27 deletions(-) >
On 12/5/2019 4:55 PM, Xiaoyao Li wrote: > On 12/2/2019 2:32 PM, Tao Xu wrote: >> This series of patches will remove MPX from Denverton, remove Remove >> monitor from some CPU models. Add additional information for -cpu help >> to indicate the changes in this version of CPU model. >> >> The output is as follows: >> x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\[" >> x86 Broadwell-v2 Intel Core Processor (Broadwell) [no TSX] >> x86 Broadwell-v3 Intel Core Processor (Broadwell) [IBRS] >> x86 Broadwell-v4 Intel Core Processor (Broadwell) [no TSX, IBRS] > > Above the changes of each Broadwell-v{2,3,4} are based on Broadwell-v1. > >> x86 Cascadelake-Server-v2 Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES] >> x86 Cascadelake-Server-v3 Intel Xeon Processor (Cascadelake) [no TSX] > > But in the code, Cascadelake-Server-v3 inherits all the features in > Cascadelake-Server-v2 and removes TSX related hle & rtm. > > So if we keep the same rule based on v1, it should be > > x86 Cascadelake-Server-v3 Intel Xeon Processor (Cascadelake) > [ARCH_CAPABILITIES, no TSX] Thank you for your suggestion. I will correct this.