Message ID | 20200420175250.25777-1-edgar.iglesias@gmail.com (mailing list archive) |
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Headers | show
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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id b73sm62831lfg.86.2020.04.20.10.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2020 10:52:51 -0700 (PDT) From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> To: qemu-devel@nongnu.org Subject: [PATCH v2 0/6] target-microblaze: Misc configurability #2 Date: Mon, 20 Apr 2020 19:52:44 +0200 Message-Id: <20200420175250.25777-1-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::243; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x243.google.com X-detected-operating-system: by eggs1p.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::243 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> |
Series |
target-microblaze: Misc configurability #2
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From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> This is another round of conversion from hardcoded regs to cpu properties. The property names are taken from the device-tree bindings. Cheers, Edgar ChangeLog: v1 -> v2: * Populate the pvr2 div-zero-exception bit Edgar E. Iglesias (6): target/microblaze: Add the opcode-0x0-illegal CPU property target/microblaze: Add the ill-opcode-exception property target/microblaze: Add the div-zero-exception property target/microblaze: Add the unaligned-exceptions property target/microblaze: Add the pvr-user1 property target/microblaze: Add the pvr-user2 property target/microblaze/cpu.c | 24 ++++++++++++++++++++++-- target/microblaze/cpu.h | 6 ++++++ target/microblaze/op_helper.c | 5 +++-- target/microblaze/translate.c | 8 ++++---- 4 files changed, 35 insertions(+), 8 deletions(-)