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[82.1.209.49]) by smtp.gmail.com with ESMTPSA id y5sm24225932wrs.63.2020.06.08.04.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2020 04:40:29 -0700 (PDT) From: Leif Lindholm To: QEMU Developers Subject: [RFC PATCH 0/3] target/arm: move common aarch64 init to helpers and make cpu max standalone Date: Mon, 8 Jun 2020 12:40:25 +0100 Message-Id: <20200608114028.25345-1-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=leif@nuviainc.com; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jones , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" As a follow-up to the thread that started with https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg01018.html Most of the a57/a53/a72 init functions is currently identical lines, with some individual options set up differently. Some of that duplication can be considered to be likely to apply to any (or at least the majoroty of) aarch64 processors to be added in the future. And finally, the "max" cpu init function currently calls the a57 one, with some non-obvious side effects including: - cpu dtb_compatible string set to "arm,cortex-a57" - kvm_target set (to A57 value) in tcg mode - id_mmfr0 containing a value present in real A57 cpus of the revision qemu emulates, but banned by the architecture specification - emulating implementation-defined cortex cp registers This series: - Creates a common initialization function for all aarch64 cpus, which also sets up the MIDR. - Creates a common initialization function for the cortex cpus defined in cpu64.h. - Detaches the "max" cpu from the A57 init, making use of both of the above helper functions. - Can definitely be split up into additional patches (especially 3/3). Leif Lindholm (3): target/arm: commonalize aarch64 cpu init target/arm: move cpu64 cortex processor common init settings to function target/arm: use cortex...common_init for cpu64 max target/arm/cpu-qom.h | 3 + target/arm/cpu64.c | 155 ++++++++++++++++++------------------------- 2 files changed, 66 insertions(+), 92 deletions(-)