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Thu, 20 May 2021 10:56:49 -0400 (EDT) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 7d490b61; Thu, 20 May 2021 14:56:47 +0000 (UTC) From: David Edmondson To: qemu-devel@nongnu.org Subject: [RFC PATCH 0/7] Support protection keys in an AMD EPYC-Milan VM Date: Thu, 20 May 2021 15:56:40 +0100 Message-Id: <20210520145647.3483809-1-david.edmondson@oracle.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" AMD EPYC-Milan CPUs introduced support for protection keys, previously available only with Intel CPUs. AMD chose to place the XSAVE state component for the protection keys at a different offset in the XSAVE state area than that chosen by Intel. To accommodate this, modify QEMU to behave appropriately on AMD systems, allowing a VM to properly take advantage of the new feature. Further, avoid manipulating XSAVE state components that are not present on AMD systems. The code in patch 6 that changes the CPUID 0x0d leaf is mostly dumped somewhere that seemed to work - I'm not sure where it really belongs. David Edmondson (7): target/i386: Declare constants for XSAVE offsets target/i386: Use constants for XSAVE offsets target/i386: Clarify the padding requirements of X86XSaveArea target/i386: Prepare for per-vendor X86XSaveArea layout target/i386: Introduce AMD X86XSaveArea sub-union target/i386: Adjust AMD XSAVE PKRU area offset in CPUID leaf 0xd target/i386: Manipulate only AMD XSAVE state on AMD target/i386/cpu.c | 19 +++++---- target/i386/cpu.h | 80 ++++++++++++++++++++++++++++-------- target/i386/kvm/kvm.c | 57 +++++++++---------------- target/i386/tcg/fpu_helper.c | 20 ++++++--- target/i386/xsave_helper.c | 70 +++++++++++++++++++------------ 5 files changed, 152 insertions(+), 94 deletions(-)