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[142.114.143.47]) by smtp.googlemail.com with ESMTPSA id z6sm7768613qke.24.2021.07.06.19.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Jul 2021 19:18:16 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com, mst@redhat.com, imammedo@redhat.com Subject: [PATCH v6 00/10] GICv3 LPI and ITS feature implementation Date: Tue, 6 Jul 2021 22:18:05 -0400 Message-Id: <20210707021815.45938-1-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: eric.auger@redhat.com, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset implements qemu device model for enabling physical LPI support and ITS functionality in GIC as per GICv3 specification. Both flat table and 2 level tables are implemented.The ITS commands for adding/deleting ITS table entries,trigerring LPI interrupts are implemented.Translated LPI interrupt ids are processed by redistributor to determine priority and set pending state appropriately before forwarding the same to cpu interface. The ITS feature support has been added to sbsa-ref platform as well as virt platform,wherein the emulated functionality co-exists with kvm kernel functionality. Changes in v6: - made changes to masking scheme being used in all relevant sections - updated process_mapti to validate idbits based on GICD_TYPER.IDbits instead of GICR_PROPBASER.IDbits - updated its_realize() to check every CPU for physical LPI support in each associated redistibutor and return error if not - removed GICR_TYPER_PLPIS check in its_reset() - addressed pending v4 comments in gicv3_internal.h #defines - refactored gicv3_redist_lpi_pending() as per v5 comments - added iasl disassembly for new IORT.pxb file - addressed all v5 comments around code formatting and gicv3_internal.h #defines - All kvm_unit_tests PASS Shashi Mallela (10): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing hw/arm/sbsa-ref: add ITS support in SBSA GIC tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS hw/arm/sbsa-ref.c | 26 +- hw/arm/virt.c | 28 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1301 ++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 154 ++- hw/intc/gicv3_internal.h | 189 +++- hw/intc/meson.build | 1 + include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- target/arm/kvm_arm.h | 4 +- tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 20 files changed, 1771 insertions(+), 27 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb