[0/3] target/riscv: Update QEmu for Zb[abcs] 1.0.0

Message

Philipp Tomsich Aug. 18, 2021, 8:08 p.m. UTC

The Zb[abcs] extensions have complete public review and are nearing
ratifications. These individual extensions are one part of what was
previously though of as the "BitManip" (B) extension, leaving the
final details of future Zb* extensions open as they will undergo
further public discourse.

This series updates the earlier support for the B extension by
 - removing those instructions that are not included in Zb[abcs]
 - splitting this into 4 separate extensions that can be independently
   enabled
 - update the to the 1.0.0 version (e.g. w-forms of rev8 and Zbs
   instructions no longer exist)



Philipp Tomsich (3):
  target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
  target/riscv: update Zb[abcs] to 1.0.0 (public review) specification
  disas/riscv: Add Zb[abcs] instructions

 disas/riscv.c                           | 157 ++++++++++-
 target/riscv/cpu.c                      |  31 +-
 target/riscv/cpu.h                      |   7 +-
 target/riscv/insn32.decode              | 119 ++++----
 target/riscv/insn_trans/trans_rvb.c.inc | 357 ++++++++++--------------
 target/riscv/translate.c                | 128 +++------
 6 files changed, 400 insertions(+), 399 deletions(-)