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Tue, 16 Nov 2021 17:01:34 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2CD66AE051; Tue, 16 Nov 2021 17:01:34 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D427EAE055; Tue, 16 Nov 2021 17:01:33 +0000 (GMT) Received: from localhost.ibm.com (unknown [9.101.4.17]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 16 Nov 2021 17:01:33 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, mst@redhat.com, marcel.apfelbaum@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/3] Fix irq allocation of PCI host bridge on powernv Date: Tue, 16 Nov 2021 18:01:30 +0100 Message-Id: <20211116170133.724751-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: VubaD4QXQwbnqNIppxw21iuW7nnDzIl7 X-Proofpoint-ORIG-GUID: snHCRcLzdMUwnhURfu5IaFXS2y_554M4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-16_03,2021-11-16_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 bulkscore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111160084 Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This series removes a bogus allocation of a LSI interrupt for the PCI Host Bridge found in the powernv model (phb4). The real hardware doesn't declare any LSI, so the model should match. It was causing some inconsistencies in the interrupt controller data. However, removing that LSI shows that the PCI AER code assumes an interrupt is defined (LSI or MSI or MSI-X), which is not the case with the root bridge device on powernv. So the last patch adds a check to make sure a LSI is defined before entering pci_set_irq() as it asserts if it's called with no LSI defined. Frederic Barrat (3): ppc/pnv: Tune the POWER9 PCIe Host bridge model pci: Export the pci_intx() function pcie_aer: Don't trigger a LSI if none are defined hw/pci-host/pnv_phb4.c | 5 ++++- hw/pci/pci.c | 5 ----- hw/pci/pcie_aer.c | 4 +++- include/hw/pci/pci.h | 5 +++++ 4 files changed, 12 insertions(+), 7 deletions(-)