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[v1,0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI

Message ID 20220130231206.34035-1-edgar.iglesias@gmail.com (mailing list archive)
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Series hw/arm: zynqmp: Add CRF and APU control to support PSCI | expand

Message

Edgar E. Iglesias Jan. 30, 2022, 11:12 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

This adds the necessary modeling to support some of our firmware
tests at EL3 implementing PSCI (TBM). These are the test-cases
that were previously relying on QEMU's builtin PSCI emulation.

I've only tested this on top of Peter's recent PSCI emulation fixes.

Cheers,
Edgar

Edgar E. Iglesias (6):
  hw/arm/xlnx-zynqmp: Add unimplemented SERDES area
  target/arm: Make rvbar settable after realize
  hw/misc: Add a model of the Xilinx ZynqMP CRF
  hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
  hw/misc: Add a model of the Xilinx ZynqMP APU Control
  hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control

 include/hw/arm/xlnx-zynqmp.h           |   4 +
 include/hw/misc/xlnx-zynqmp-apu-ctrl.h |  91 +++++++++
 include/hw/misc/xlnx-zynqmp-crf.h      | 209 +++++++++++++++++++
 hw/arm/xlnx-zynqmp.c                   |  45 ++++-
 hw/misc/xlnx-zynqmp-apu-ctrl.c         | 257 +++++++++++++++++++++++
 hw/misc/xlnx-zynqmp-crf.c              | 270 +++++++++++++++++++++++++
 target/arm/cpu.c                       |   7 +-
 hw/misc/meson.build                    |   2 +
 8 files changed, 879 insertions(+), 6 deletions(-)
 create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
 create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
 create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
 create mode 100644 hw/misc/xlnx-zynqmp-crf.c