| Message ID | 20220428094708.84835-1-david@redhat.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | s390x/tcg: Implement Vector-Enhancements Facility 2 | expand |
On 28/04/2022 11.46, David Hildenbrand wrote: > Implement Vector-Enhancements Facility 2 for s390x > > resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > > implements: > VECTOR LOAD ELEMENTS REVERSED (VLER) > VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) > VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > VECTOR STORE ELEMENTS REVERSED (VSTER) > VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) > VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) > VECTOR STRING SEARCH (VSTRS) > > modifies: > VECTOR FP CONVERT FROM FIXED (VCFPS) > VECTOR FP CONVERT FROM LOGICAL (VCFPL) > VECTOR FP CONVERT TO FIXED (VCSFP) > VECTOR FP CONVERT TO LOGICAL (VCLFP) > VECTOR SHIFT LEFT (VSL) > VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > VECTOR SHIFT RIGHT LOGICAL (VSRL) Thanks, queued to my s390x-next branch now: https://gitlab.com/thuth/qemu/-/commits/s390x-next/ Thomas
On 02.05.22 09:20, Thomas Huth wrote: > On 28/04/2022 11.46, David Hildenbrand wrote: >> Implement Vector-Enhancements Facility 2 for s390x >> >> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 >> >> implements: >> VECTOR LOAD ELEMENTS REVERSED (VLER) >> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) >> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) >> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) >> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) >> VECTOR STORE ELEMENTS REVERSED (VSTER) >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) >> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) >> VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) >> VECTOR STRING SEARCH (VSTRS) >> >> modifies: >> VECTOR FP CONVERT FROM FIXED (VCFPS) >> VECTOR FP CONVERT FROM LOGICAL (VCFPL) >> VECTOR FP CONVERT TO FIXED (VCSFP) >> VECTOR FP CONVERT TO LOGICAL (VCLFP) >> VECTOR SHIFT LEFT (VSL) >> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) >> VECTOR SHIFT RIGHT LOGICAL (VSRL) > > Thanks, queued to my s390x-next branch now: > > https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > Thanks for fixing up. At this point I would have suggested to exclude the tests for now.
There was also the patch that had them as .insn in the other series of emails. On Mon, May 2, 2022 at 11:52 AM David Hildenbrand <david@redhat.com> wrote: > > On 02.05.22 09:20, Thomas Huth wrote: > > On 28/04/2022 11.46, David Hildenbrand wrote: > >> Implement Vector-Enhancements Facility 2 for s390x > >> > >> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > >> > >> implements: > >> VECTOR LOAD ELEMENTS REVERSED (VLER) > >> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > >> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) > >> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > >> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > >> VECTOR STORE ELEMENTS REVERSED (VSTER) > >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > >> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) > >> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > >> VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) > >> VECTOR STRING SEARCH (VSTRS) > >> > >> modifies: > >> VECTOR FP CONVERT FROM FIXED (VCFPS) > >> VECTOR FP CONVERT FROM LOGICAL (VCFPL) > >> VECTOR FP CONVERT TO FIXED (VCSFP) > >> VECTOR FP CONVERT TO LOGICAL (VCLFP) > >> VECTOR SHIFT LEFT (VSL) > >> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > >> VECTOR SHIFT RIGHT LOGICAL (VSRL) > > > > Thanks, queued to my s390x-next branch now: > > > > https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > > > Thanks for fixing up. At this point I would have suggested to exclude > the tests for now. > > -- > Thanks, > > David / dhildenb >
Hi! On 02/05/2022 18.06, David Miller wrote: > There was also the patch that had them as .insn in the other series of emails. Sorry, I missed that patch, could you please point me to the mail on https://lore.kernel.org/qemu-devel/ ? I remember that there was a discussion about the vri-d encoding, but I apparently missed the patch that came out of this discussion... Thomas > On Mon, May 2, 2022 at 11:52 AM David Hildenbrand <david@redhat.com> wrote: >> >> On 02.05.22 09:20, Thomas Huth wrote: >>> On 28/04/2022 11.46, David Hildenbrand wrote: >>>> Implement Vector-Enhancements Facility 2 for s390x >>>> >>>> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 >>>> >>>> implements: >>>> VECTOR LOAD ELEMENTS REVERSED (VLER) >>>> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) >>>> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) >>>> VECTOR STORE ELEMENTS REVERSED (VSTER) >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) >>>> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) >>>> VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) >>>> VECTOR STRING SEARCH (VSTRS) >>>> >>>> modifies: >>>> VECTOR FP CONVERT FROM FIXED (VCFPS) >>>> VECTOR FP CONVERT FROM LOGICAL (VCFPL) >>>> VECTOR FP CONVERT TO FIXED (VCSFP) >>>> VECTOR FP CONVERT TO LOGICAL (VCLFP) >>>> VECTOR SHIFT LEFT (VSL) >>>> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) >>>> VECTOR SHIFT RIGHT LOGICAL (VSRL) >>> >>> Thanks, queued to my s390x-next branch now: >>> >>> https://gitlab.com/thuth/qemu/-/commits/s390x-next/ >>> >> Thanks for fixing up. At this point I would have suggested to exclude >> the tests for now. >> >> -- >> Thanks, >> >> David / dhildenb >> >
Sorry, It was in the discussion for v4 patches, as an attachment . mail thread: [PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2 So it likely never made it to the mailing list. I've reattached and will forward the patch (by itself) to the mailing list. I think the other solution works just as well by ignoring if compiler doesn't support z15. I just thought I'd bring it back up as I saw discussion about it. Thanks - David Miller On Tue, May 3, 2022 at 2:55 AM Thomas Huth <thuth@redhat.com> wrote: > > Hi! > > On 02/05/2022 18.06, David Miller wrote: > > There was also the patch that had them as .insn in the other series of emails. > > Sorry, I missed that patch, could you please point me to the mail on > https://lore.kernel.org/qemu-devel/ ? I remember that there was a discussion > about the vri-d encoding, but I apparently missed the patch that came out of > this discussion... > > Thomas > > > On Mon, May 2, 2022 at 11:52 AM David Hildenbrand <david@redhat.com> wrote: > >> > >> On 02.05.22 09:20, Thomas Huth wrote: > >>> On 28/04/2022 11.46, David Hildenbrand wrote: > >>>> Implement Vector-Enhancements Facility 2 for s390x > >>>> > >>>> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > >>>> > >>>> implements: > >>>> VECTOR LOAD ELEMENTS REVERSED (VLER) > >>>> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > >>>> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > >>>> VECTOR STORE ELEMENTS REVERSED (VSTER) > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) > >>>> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > >>>> VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) > >>>> VECTOR STRING SEARCH (VSTRS) > >>>> > >>>> modifies: > >>>> VECTOR FP CONVERT FROM FIXED (VCFPS) > >>>> VECTOR FP CONVERT FROM LOGICAL (VCFPL) > >>>> VECTOR FP CONVERT TO FIXED (VCSFP) > >>>> VECTOR FP CONVERT TO LOGICAL (VCLFP) > >>>> VECTOR SHIFT LEFT (VSL) > >>>> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > >>>> VECTOR SHIFT RIGHT LOGICAL (VSRL) > >>> > >>> Thanks, queued to my s390x-next branch now: > >>> > >>> https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > >>> > >> Thanks for fixing up. At this point I would have suggested to exclude > >> the tests for now. > >> > >> -- > >> Thanks, > >> > >> David / dhildenb > >> > > >
It looks like google killed allowing password access early, nothing makes it work anymore. They had plans to disable 'less secure app' in may, but it thought it was the end of the month. I'll try copy/paste as plain text as well though I Know it will likely screw it up.. On Tue, May 3, 2022 at 10:42 AM David Miller <dmiller423@gmail.com> wrote: > > Sorry, It was in the discussion for v4 patches, as an attachment . > mail thread: > [PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2 > So it likely never made it to the mailing list. > > I've reattached and will forward the patch (by itself) to the mailing list. > > I think the other solution works just as well by ignoring if compiler > doesn't support z15. > > I just thought I'd bring it back up as I saw discussion about it. > > Thanks > - David Miller > > > > > > > On Tue, May 3, 2022 at 2:55 AM Thomas Huth <thuth@redhat.com> wrote: > > > > Hi! > > > > On 02/05/2022 18.06, David Miller wrote: > > > There was also the patch that had them as .insn in the other series of emails. > > > > Sorry, I missed that patch, could you please point me to the mail on > > https://lore.kernel.org/qemu-devel/ ? I remember that there was a discussion > > about the vri-d encoding, but I apparently missed the patch that came out of > > this discussion... > > > > Thomas > > > > > On Mon, May 2, 2022 at 11:52 AM David Hildenbrand <david@redhat.com> wrote: > > >> > > >> On 02.05.22 09:20, Thomas Huth wrote: > > >>> On 28/04/2022 11.46, David Hildenbrand wrote: > > >>>> Implement Vector-Enhancements Facility 2 for s390x > > >>>> > > >>>> resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 > > >>>> > > >>>> implements: > > >>>> VECTOR LOAD ELEMENTS REVERSED (VLER) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) > > >>>> VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) > > >>>> VECTOR STORE ELEMENTS REVERSED (VSTER) > > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) > > >>>> VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) > > >>>> VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) > > >>>> VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) > > >>>> VECTOR STRING SEARCH (VSTRS) > > >>>> > > >>>> modifies: > > >>>> VECTOR FP CONVERT FROM FIXED (VCFPS) > > >>>> VECTOR FP CONVERT FROM LOGICAL (VCFPL) > > >>>> VECTOR FP CONVERT TO FIXED (VCSFP) > > >>>> VECTOR FP CONVERT TO LOGICAL (VCLFP) > > >>>> VECTOR SHIFT LEFT (VSL) > > >>>> VECTOR SHIFT RIGHT ARITHMETIC (VSRA) > > >>>> VECTOR SHIFT RIGHT LOGICAL (VSRL) > > >>> > > >>> Thanks, queued to my s390x-next branch now: > > >>> > > >>> https://gitlab.com/thuth/qemu/-/commits/s390x-next/ > > >>> > > >> Thanks for fixing up. At this point I would have suggested to exclude > > >> the tests for now. > > >> > > >> -- > > >> Thanks, > > >> > > >> David / dhildenb > > >> > > > > >
From bb6bf2f9529c4d76db9a9eff2ff7fa1235657103 Mon Sep 17 00:00:00 2001 From: David Miller <dmiller423@gmail.com> Date: Mon, 21 Mar 2022 16:58:57 -0400 Subject: [PATCH v5 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2 Signed-off-by: David Miller <dmiller423@gmail.com> --- tests/tcg/s390x/Makefile.target | 8 ++ tests/tcg/s390x/vx.h | 19 +++++ tests/tcg/s390x/vxeh2_vcvt.c | 88 ++++++++++++++++++++ tests/tcg/s390x/vxeh2_vlstr.c | 139 ++++++++++++++++++++++++++++++++ tests/tcg/s390x/vxeh2_vs.c | 95 ++++++++++++++++++++++ 5 files changed, 349 insertions(+) create mode 100644 tests/tcg/s390x/vx.h create mode 100644 tests/tcg/s390x/vxeh2_vcvt.c create mode 100644 tests/tcg/s390x/vxeh2_vlstr.c create mode 100644 tests/tcg/s390x/vxeh2_vs.c diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index 8c9b6a13ce..921a056dd1 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -16,6 +16,14 @@ TESTS+=shift TESTS+=trap TESTS+=signals-s390x +VECTOR_TESTS=vxeh2_vs +VECTOR_TESTS+=vxeh2_vcvt +VECTOR_TESTS+=vxeh2_vlstr + +TESTS+=$(VECTOR_TESTS) + +$(VECTOR_TESTS): CFLAGS+=-march=z15 -O2 + ifneq ($(HAVE_GDB_BIN),) GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py diff --git a/tests/tcg/s390x/vx.h b/tests/tcg/s390x/vx.h new file mode 100644 index 0000000000..2e66f8b714 --- /dev/null +++ b/tests/tcg/s390x/vx.h @@ -0,0 +1,19 @@ +#ifndef QEMU_TESTS_S390X_VX_H +#define QEMU_TESTS_S390X_VX_H + +typedef union S390Vector { + uint64_t d[2]; /* doubleword */ + uint32_t w[4]; /* word */ + uint16_t h[8]; /* halfword */ + uint8_t b[16]; /* byte */ + float f[4]; /* float32 */ + double fd[2]; /* float64 */ + __uint128_t v; +} S390Vector; + +#define ES8 0 +#define ES16 1 +#define ES32 2 +#define ES64 3 + +#endif \ No newline at end of file diff --git a/tests/tcg/s390x/vxeh2_vcvt.c b/tests/tcg/s390x/vxeh2_vcvt.c new file mode 100644 index 0000000000..2e46841ab5 --- /dev/null +++ b/tests/tcg/s390x/vxeh2_vcvt.c @@ -0,0 +1,88 @@ +/* + * vxeh2_vcvt: vector-enhancements facility 2 vector convert * + */ +#include <stdint.h> +#include "vx.h" + +#define M_S 8 +#define M4_XxC 4 +#define M4_def M4_XxC + +static inline void vcfps(S390Vector *v1, S390Vector *v2, + const uint8_t m3, const uint8_t m4, const uint8_t m5) +{ + asm volatile(".insn vrr, 0xE700000000C3, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [m3] "i" (m3) + , [m4] "i" (m4) + , [m5] "i" (m5)); +} + +static inline void vcfpl(S390Vector *v1, S390Vector *v2, + const uint8_t m3, const uint8_t m4, const uint8_t m5) +{ + asm volatile(".insn vrr, 0xE700000000C1, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [m3] "i" (m3) + , [m4] "i" (m4) + , [m5] "i" (m5)); +} + +static inline void vcsfp(S390Vector *v1, S390Vector *v2, + const uint8_t m3, const uint8_t m4, const uint8_t m5) +{ + asm volatile(".insn vrr, 0xE700000000C2, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [m3] "i" (m3) + , [m4] "i" (m4) + , [m5] "i" (m5)); +} + +static inline void vclfp(S390Vector *v1, S390Vector *v2, + const uint8_t m3, const uint8_t m4, const uint8_t m5) +{ + asm volatile(".insn vrr, 0xE700000000C0, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [m3] "i" (m3) + , [m4] "i" (m4) + , [m5] "i" (m5)); +} + +int main(int argc, char *argv[]) +{ + S390Vector vd; + S390Vector vs_i32 = { .w[0] = 1, .w[1] = 64, .w[2] = 1024, .w[3] = -10 }; + S390Vector vs_u32 = { .w[0] = 2, .w[1] = 32, .w[2] = 4096, .w[3] = 8888 }; + S390Vector vs_f32 = { .f[0] = 3.987, .f[1] = 5.123, + .f[2] = 4.499, .f[3] = 0.512 }; + + vd.d[0] = vd.d[1] = 0; + vcfps(&vd, &vs_i32, 2, M4_def, 0); + if (1 != vd.f[0] || 1024 != vd.f[2] || 64 != vd.f[1] || -10 != vd.f[3]) { + return 1; + } + + vd.d[0] = vd.d[1] = 0; + vcfpl(&vd, &vs_u32, 2, M4_def, 0); + if (2 != vd.f[0] || 4096 != vd.f[2] || 32 != vd.f[1] || 8888 != vd.f[3]) { + return 1; + } + + vd.d[0] = vd.d[1] = 0; + vcsfp(&vd, &vs_f32, 2, M4_def, 0); + if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 != vd.w[3]) { + return 1; + } + + vd.d[0] = vd.d[1] = 0; + vclfp(&vd, &vs_f32, 2, M4_def, 0); + if (4 != vd.w[0] || 4 != vd.w[2] || 5 != vd.w[1] || 1 != vd.w[3]) { + return 1; + } + + return 0; +} diff --git a/tests/tcg/s390x/vxeh2_vlstr.c b/tests/tcg/s390x/vxeh2_vlstr.c new file mode 100644 index 0000000000..770691a4e8 --- /dev/null +++ b/tests/tcg/s390x/vxeh2_vlstr.c @@ -0,0 +1,139 @@ +/* + * vxeh2_vlstr: vector-enhancements facility 2 vector load/store reversed * + */ +#include <stdint.h> +#include "vx.h" + +#define vtst(v1, v2) \ + if (v1.d[0] != v2.d[0] || v1.d[1] != v2.d[1]) { \ + return 1; \ + } + +static inline void vler(S390Vector *v1, const void *va, uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000007, %[v1], 0(%[va]), %[m3]\n" + : [v1] "+v" (v1->v) + : [va] "d" (va) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vster(S390Vector *v1, const void *va, uint8_t m3) +{ + asm volatile(".insn vrx, 0xE6000000000F, %[v1], 0(%[va]), %[m3]\n" + : [va] "+d" (va) + : [v1] "v" (v1->v) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vlbr(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000006, %[v1], 0(%[va]), %[m3]\n" + : [v1] "+v" (v1->v) + : [va] "d" (va) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vstbr(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE6000000000E, %[v1], 0(%[va]), %[m3]\n" + : [va] "+d" (va) + : [v1] "v" (v1->v) + , [m3] "i" (m3) + : "memory"); +} + + +static inline void vlebrh(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000001, %[v1], 0(%[va]), %[m3]\n" + : [v1] "+v" (v1->v) + : [va] "d" (va) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vstebrh(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000009, %[v1], 0(%[va]), %[m3]\n" + : [va] "+d" (va) + : [v1] "v" (v1->v) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vllebrz(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000004, %[v1], 0(%[va]), %[m3]\n" + : [v1] "+v" (v1->v) + : [va] "d" (va) + , [m3] "i" (m3) + : "memory"); +} + +static inline void vlbrrep(S390Vector *v1, void *va, const uint8_t m3) +{ + asm volatile(".insn vrx, 0xE60000000005, %[v1], 0(%[va]), %[m3]\n" + : [v1] "+v" (v1->v) + : [va] "d" (va) + , [m3] "i" (m3) + : "memory"); +} + +int main(int argc, char *argv[]) +{ + S390Vector vd = { .d[0] = 0, .d[1] = 0 }; + S390Vector vs = { .d[0] = 0x8FEEDDCCBBAA9988ull, + .d[1] = 0x7766554433221107ull }; + + const S390Vector vt_v_er16 = { + .h[0] = 0x1107, .h[1] = 0x3322, .h[2] = 0x5544, .h[3] = 0x7766, + .h[4] = 0x9988, .h[5] = 0xBBAA, .h[6] = 0xDDCC, .h[7] = 0x8FEE }; + + const S390Vector vt_v_br16 = { + .h[0] = 0xEE8F, .h[1] = 0xCCDD, .h[2] = 0xAABB, .h[3] = 0x8899, + .h[4] = 0x6677, .h[5] = 0x4455, .h[6] = 0x2233, .h[7] = 0x0711 }; + + int ix; + uint64_t ss64 = 0xFEEDFACE0BADBEEFull, sd64 = 0; + + vler(&vd, &vs, ES16); + vtst(vd, vt_v_er16); + + vster(&vs, &vd, ES16); + vtst(vd, vt_v_er16); + + vlbr(&vd, &vs, ES16); + vtst(vd, vt_v_br16); + + vstbr(&vs, &vd, ES16); + vtst(vd, vt_v_br16); + + vlebrh(&vd, &ss64, 5); + if (0xEDFE != vd.h[5]) { + return 1; + } + + vstebrh(&vs, (uint8_t *)&sd64 + 4, 7); + if (0x0000000007110000ull != sd64) { + return 1; + } + + vllebrz(&vd, (uint8_t *)&ss64 + 3, 2); + for (ix = 0; ix < 4; ix++) { + if (vd.w[ix] != (ix != 1 ? 0 : 0xBEAD0BCE)) { + return 1; + } + } + + vlbrrep(&vd, (uint8_t *)&ss64 + 4, 1); + for (ix = 0; ix < 8; ix++) { + if (0xAD0B != vd.h[ix]) { + return 1; + } + } + + return 0; +} diff --git a/tests/tcg/s390x/vxeh2_vs.c b/tests/tcg/s390x/vxeh2_vs.c new file mode 100644 index 0000000000..78f5c9a8be --- /dev/null +++ b/tests/tcg/s390x/vxeh2_vs.c @@ -0,0 +1,95 @@ +/* + * vxeh2_vs: vector-enhancements facility 2 vector shift + */ +#include <stdint.h> +#include "vx.h" + +#define vtst(v1, v2) \ + if (v1.d[0] != v2.d[0] || v1.d[1] != v2.d[1]) { \ + return 1; \ + } + +static inline void vsl(S390Vector *v1, S390Vector *v2, S390Vector *v3) +{ + asm volatile(".insn vrr, 0xE70000000074, %[v1], %[v2], %[v3], 0,0,0\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [v3] "v" (v3->v)); +} + +static inline void vsra(S390Vector *v1, S390Vector *v2, S390Vector *v3) +{ + asm volatile(".insn vrr, 0xE7000000007E, %[v1], %[v2], %[v3], 0,0,0\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [v3] "v" (v3->v)); +} + +static inline void vsrl(S390Vector *v1, S390Vector *v2, S390Vector *v3) +{ + asm volatile(".insn vrr, 0xE7000000007C, %[v1], %[v2], %[v3], 0,0,0\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [v3] "v" (v3->v)); +} + +static inline void vsld(S390Vector *v1, S390Vector *v2, + S390Vector *v3, const uint8_t I) +{ + /* vri-d as vrr */ + asm volatile(".insn vrr, 0xE70000000086, %[v1], %[v2], %[v3], 0, %[I], 0\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [v3] "v" (v3->v) + , [I] "i" (I & 7)); +} + +static inline void vsrd(S390Vector *v1, S390Vector *v2, + S390Vector *v3, const uint8_t I) +{ + /* vri-d as vrr */ + asm volatile(".insn vrr, 0xE70000000087, %[v1], %[v2], %[v3], 0, %[I], 0\n" + : [v1] "=v" (v1->v) + : [v2] "v" (v2->v) + , [v3] "v" (v3->v) + , [I] "i" (I & 7)); +} + +int main(int argc, char *argv[]) +{ + const S390Vector vt_vsl = { .d[0] = 0x7FEDBB32D5AA311Dull, + .d[1] = 0xBB65AA10912220C0ull }; + const S390Vector vt_vsra = { .d[0] = 0xF1FE6E7399AA5466ull, + .d[1] = 0x0E762A5188221044ull }; + const S390Vector vt_vsrl = { .d[0] = 0x11FE6E7399AA5466ull, + .d[1] = 0x0E762A5188221044ull }; + const S390Vector vt_vsld = { .d[0] = 0x7F76EE65DD54CC43ull, + .d[1] = 0xBB32AA2199108838ull }; + const S390Vector vt_vsrd = { .d[0] = 0x0E060802040E000Aull, + .d[1] = 0x0C060802040E000Aull }; + S390Vector vs = { .d[0] = 0x8FEEDDCCBBAA9988ull, + .d[1] = 0x7766554433221107ull }; + S390Vector vd = { .d[0] = 0, .d[1] = 0 }; + S390Vector vsi = { .d[0] = 0, .d[1] = 0 }; + + for (int ix = 0; ix < 16; ix++) { + vsi.b[ix] = (1 + (5 ^ ~ix)) & 7; + } + + vsl(&vd, &vs, &vsi); + vtst(vd, vt_vsl); + + vsra(&vd, &vs, &vsi); + vtst(vd, vt_vsra); + + vsrl(&vd, &vs, &vsi); + vtst(vd, vt_vsrl); + + vsld(&vd, &vs, &vsi, 3); + vtst(vd, vt_vsld); + + vsrd(&vd, &vs, &vsi, 15); + vtst(vd, vt_vsrd); + + return 0; +}
On 03/05/2022 16.57, David Miller wrote: > It looks like google killed allowing password access early, nothing > makes it work anymore. Uh, that's ugly! I hope you'll figure out a way to work-around that problem! > They had plans to disable 'less secure app' in may, but it thought it > was the end of the month. > I'll try copy/paste as plain text as well though I Know it will likely > screw it up.. Yup, that plain text patch didn't apply anymore - so I went for the attachment from your previous mail this time instead (hoping that you'll find another way for using git-send-email again in the future). Thomas
On 03/05/2022 16.42, David Miller wrote: > Sorry, It was in the discussion for v4 patches, as an attachment . > mail thread: > [PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2 > So it likely never made it to the mailing list. > > I've reattached and will forward the patch (by itself) to the mailing list. > > I think the other solution works just as well by ignoring if compiler > doesn't support z15. > > I just thought I'd bring it back up as I saw discussion about it. Ok, I now gave this a try ... and while this should now work fine with older versions of gcc/binutils, it's failing with Clang now: BUILD s390x-linux-user guest-tests /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vs.c:14:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE70000000074, %[v1], %[v2], %[v3], 0,0,0\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vs.c:22:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE7000000007E, %[v1], %[v2], %[v3], 0,0,0\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vs.c:30:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE7000000007C, %[v1], %[v2], %[v3], 0,0,0\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vs.c:40:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE70000000086, %[v1], %[v2], %[v3], 0, %[I], 0\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vs.c:51:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE70000000087, %[v1], %[v2], %[v3], 0, %[I], 0\n" ^ 5 errors generated. make[1]: *** [../Makefile.target:109: vxeh2_vs] Error 1 make[1]: *** Waiting for unfinished jobs.... /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vcvt.c:14:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE700000000C3, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vcvt.c:25:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE700000000C1, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vcvt.c:36:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE700000000C2, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" ^ /home/thuth/devel/qemu/tests/tcg/s390x/vxeh2_vcvt.c:47:18: error: couldn't allocate output register for constraint 'v' asm volatile(".insn vrr, 0xE700000000C0, %[v1], %[v2], 0, %[m3], %[m4], %[m5]\n" ^ 4 errors generated. ... Thus I think I'll rather go with the other approach instead that checks for the availability of -march=z15. Thomas
Implement Vector-Enhancements Facility 2 for s390x resolves: https://gitlab.com/qemu-project/qemu/-/issues/738 implements: VECTOR LOAD ELEMENTS REVERSED (VLER) VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR) VECTOR LOAD BYTE REVERSED ELEMENT (VLEBRH, VLEBRF, VLEBRG) VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ) VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP) VECTOR STORE ELEMENTS REVERSED (VSTER) VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR) VECTOR STORE BYTE REVERSED ELEMENTS (VSTEBRH, VSTEBRF, VSTEBRG) VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD) VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD) VECTOR STRING SEARCH (VSTRS) modifies: VECTOR FP CONVERT FROM FIXED (VCFPS) VECTOR FP CONVERT FROM LOGICAL (VCFPL) VECTOR FP CONVERT TO FIXED (VCSFP) VECTOR FP CONVERT TO LOGICAL (VCLFP) VECTOR SHIFT LEFT (VSL) VECTOR SHIFT RIGHT ARITHMETIC (VSRA) VECTOR SHIFT RIGHT LOGICAL (VSRL) v5 -> v6: * Move fix to #1 * Include max CPU model cleanups * "target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model" -> Take care of compat machines * "tests/tcg/s390x: Tests for Vector Enhancements Facility 2" -> Add missing newline to end of header file -> Resolve simple conflict in Makefile Cc: Thomas Huth <thuth@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: David Miller <dmiller423@gmail.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Cornelia Huck <cohuck@redhat.com> Cc: Halil Pasic <pasic@linux.ibm.com> Cc: Eric Farman <farman@linux.ibm.com> David Hildenbrand (2): s390x/cpu_models: drop "msa5" from the TCG "max" model s390x/cpu_models: make "max" match the unmodified "qemu" CPU model under TCG David Miller (9): target/s390x: vxeh2: vector convert short/32b target/s390x: vxeh2: vector string search target/s390x: vxeh2: Update for changes to vector shifts target/s390x: vxeh2: vector shift double by bit target/s390x: vxeh2: vector {load, store} elements reversed target/s390x: vxeh2: vector {load, store} byte reversed elements target/s390x: vxeh2: vector {load, store} byte reversed element target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model tests/tcg/s390x: Tests for Vector Enhancements Facility 2 Richard Henderson (2): target/s390x: Fix writeback to v1 in helper_vstl tcg: Implement tcg_gen_{h,w}swap_{i32,i64} hw/s390x/s390-virtio-ccw.c | 3 + include/tcg/tcg-op.h | 6 + target/s390x/cpu_models.c | 26 +- target/s390x/gen-features.c | 14 +- target/s390x/helper.h | 13 + target/s390x/tcg/insn-data.def | 40 ++- target/s390x/tcg/translate.c | 3 +- target/s390x/tcg/translate_vx.c.inc | 461 ++++++++++++++++++++++++--- target/s390x/tcg/vec_fpu_helper.c | 31 ++ target/s390x/tcg/vec_helper.c | 2 - target/s390x/tcg/vec_int_helper.c | 55 ++++ target/s390x/tcg/vec_string_helper.c | 99 ++++++ tcg/tcg-op.c | 30 ++ tests/tcg/s390x/Makefile.target | 8 + tests/tcg/s390x/vx.h | 19 ++ tests/tcg/s390x/vxeh2_vcvt.c | 88 +++++ tests/tcg/s390x/vxeh2_vlstr.c | 139 ++++++++ tests/tcg/s390x/vxeh2_vs.c | 93 ++++++ 18 files changed, 1051 insertions(+), 79 deletions(-) create mode 100644 tests/tcg/s390x/vx.h create mode 100644 tests/tcg/s390x/vxeh2_vcvt.c create mode 100644 tests/tcg/s390x/vxeh2_vlstr.c create mode 100644 tests/tcg/s390x/vxeh2_vs.c