From patchwork Mon May 9 12:48:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?V=C3=ADctor_Colombo?= X-Patchwork-Id: 12843572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F64FC433F5 for ; Mon, 9 May 2022 13:24:26 +0000 (UTC) Received: from localhost ([::1]:44248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no3NB-0006Jr-JO for qemu-devel@archiver.kernel.org; Mon, 09 May 2022 09:24:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no2qH-0003qI-BE; Mon, 09 May 2022 08:50:25 -0400 Received: from [187.72.171.209] (port=40533 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2qF-0002Fj-EH; Mon, 09 May 2022 08:50:24 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Mon, 9 May 2022 09:49:17 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id ECAF9800068; Mon, 9 May 2022 09:49:16 -0300 (-03) From: =?utf-8?q?V=C3=ADctor_Colombo?= To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, victor.colombo@eldorado.org.br Subject: [PATCH 0/2] target/ppc: Fix FPSCR.FI bit Date: Mon, 9 May 2022 09:48:34 -0300 Message-Id: <20220509124836.27819-1-victor.colombo@eldorado.org.br> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-OriginalArrivalTime: 09 May 2022 12:49:17.0655 (UTC) FILETIME=[31F77670:01D863A3] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass client-ip=187.72.171.209; envelope-from=victor.colombo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hello everyone, The FI bit in FPSCR is said to be a non-sticky bit on Power ISA. One could think this means that, if an instruction is said to modify the FPSCR register, the bit FI should be cleared. This is what QEMU does today. This is not, however, what the real hardware appears to do. It looks like QEMU's interpretation of Power ISA was not correct for the implementation of this bit. This patch set fixes inconsistencies found in QEMU's handling of the FPSCR.FI bit. I found this while investigating how to enable Hardfpu for Power guests. This change in the understanding on how the Power arch handles the inexact bit makes it trivial to enable hardfpu for affected instructions (mostly vsx-vector), but actually seems to create even more complexity for the changes that will be required to enable hardfpu for all float instructions. I'll instigate this discussion more in the next few weeks. Thanks! Víctor Colombo (2): target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't target/ppc: Fix FPSCR.FI changing in float_overflow_excp() target/ppc/fpu_helper.c | 213 +++++++++++++++++++++------------------- 1 file changed, 111 insertions(+), 102 deletions(-)