[v2,0/3] target/ppc: Fix FPSCR.FI bit

Message

Víctor Colombo May 10, 2022, 8:46 p.m. UTC

Hello everyone,

The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.

This is not, however, what the real hardware appears to do. It looks
like QEMU's interpretation of Power ISA was not correct for the
implementation of this bit.

This patch set fixes inconsistencies found in QEMU's handling of the
FPSCR.FI bit.

I found this while investigating how to enable Hardfpu for Power
guests. This change in the understanding on how the Power arch
handles the inexact bit makes it trivial to enable hardfpu for
affected instructions (mostly vsx-vector), but actually seems to
create even more complexity for the changes that will be required
to enable hardfpu for all float instructions. I'll instigate this
discussion more in the next few weeks.

Thanks!

v2:
- move the FI change from float_inexact_excp to do_float_check_status
- remove the setting of FI from float_overflow_excp, making
  do_float_check_status() the only responsible for it.
- make float_overflow_excp() return float_flag_inexact if it should
  update the inexact flags.
- Add patch 3, moving the renaming of sfprf to sfifprf to it
  (previously on patch 1)

Víctor Colombo (3):
  target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't
  target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
  target/ppc: Rename sfprf to sfifprf where it's also used as set fi
    flag

 target/ppc/cpu.h        |   2 +
 target/ppc/fpu_helper.c | 223 +++++++++++++++++++++-------------------
 2 files changed, 117 insertions(+), 108 deletions(-)