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[RFC,0/2] target/ppc: Propose rework in fp exception handling

Message ID 20220512194250.138244-1-victor.colombo@eldorado.org.br (mailing list archive)
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Series target/ppc: Propose rework in fp exception handling | expand

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Víctor Colombo May 12, 2022, 7:42 p.m. UTC 
Hello everyone!

I would like to propose a rework on the fpscr exceptions in
fpu_helper.c. Today, we have: do_float_check_status() dealing with
Overflow, Underflow, and Inexact; and other helpers for the invalid
exceptions (like float_invalid_op_vximz(), float_invalid_op_vxisi()),
including some special cases like float_invalid_op_madd(). So, there is
a lot of helpers that may need to be used in the insn helpers code.

My idea is try to find a way to concentrate them in a single place.
This RFC moves imz, isi, and snan excp helpers to do_float_check_status
as a hub for dealing with the commitment of exception flags from
env->fp_status to env->fpscr. Then, show how an instruction could
benefit of this change by adapting VSX_MADD helper to leverage the
changes.

The main objectives with this patch set are:
1. Try to simplify the excp handling code.
2. Allow for MMA instruction XVFGER to be easily implemented
   (see [1])

This RFC is just a subset of what I think should be done. There are
more exceptions to be moved to do_float_check_status, and many more
instructions to refactor to use it.

Thanks!

Based-on the FI bit fix [2].

[1] https://lists.gnu.org/archive/html/qemu-ppc/2022-05/msg00176.html
[2] <20220510204610.100867-1-victor.colombo@eldorado.org.br>
    https://lists.nongnu.org/archive/html/qemu-ppc/2022-05/msg00246.html
    https://patchew.org/QEMU/20220510204610.100867-1-victor.colombo@eldorado.org.br/

Víctor Colombo (2):
  target/ppc: Add invalid imz, isi and snan to do_float_check_status()
  target/ppc: Rely on do_float_check_status for VSX_MADD invalid excepts

 target/ppc/fpu_helper.c | 148 ++++++++++++++++++++++++++--------------
 1 file changed, 97 insertions(+), 51 deletions(-)