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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id i13-20020a170902c94d00b0016362da9a03sm17853534pla.245.2022.06.09.22.13.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 22:13:32 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang Subject: [PATCH 0/9] Improve RISC-V Debug support Date: Fri, 10 Jun 2022 13:13:17 +0800 Message-Id: <20220610051328.7078-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang This patchset refactors RISC-V Debug support to allow more types of triggers to be extended. The initial support of type 6 trigger, which is similar to type 2 trigger with additional functionality, is also introduced in this patchset. Frank Chang (9): target/riscv: debug: Determine the trigger type from tdata1.type target/riscv: debug: Introduce build_tdata1() to build tdata1 register content target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs target/riscv: debug: Restrict the range of tselect value can be written target/riscv: debug: Introduce tinfo CSR target/riscv: debug: Create common trigger actions function target/riscv: debug: Check VU/VS modes for type 2 trigger target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers target/riscv: debug: Add initial support of type 6 trigger target/riscv/cpu.h | 7 +- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 10 +- target/riscv/debug.c | 483 ++++++++++++++++++++++++++++++++-------- target/riscv/debug.h | 55 +++-- target/riscv/machine.c | 20 +- 6 files changed, 445 insertions(+), 131 deletions(-) --- 2.36.1