| Message ID | 20220713165458.58807-1-victor.colombo@eldorado.org.br (mailing list archive) |
|---|---|
| Headers | show |
| Series | Implement Power ISA 3.1B hash insns | expand |
On 7/13/22 13:54, Víctor Colombo wrote: > This patch series implements the 4 instructions added in Power ISA > 3.1B: > > - hashchk > - hashst > - hashchkp > - hashstp > > To build it, you need to apply the following patches on top of master: > <20220701133507.740619-2-lucas.coutinho@eldorado.org.br> > <20220701133507.740619-3-lucas.coutinho@eldorado.org.br> > <20220712193741.59134-2-leandro.lupori@eldorado.org.br> > <20220712193741.59134-3-leandro.lupori@eldorado.org.br> > > Working branch for ease of use can be found here: > https://github.com/PPC64/qemu/tree/vccolombo-hash-to-send-v3 > > What do you think about the choice to implement the hash algorithm > from the ground up, following the SIMON-like algorithm presented in > Power ISA? IIUC, this algorithm is not the same as the original[1]. > Other options would be to use other algorithm already implemented > in QEMU, or even make this instruction a nop for all Power versions. > > Also, I was thinking about using the call to spr_register_kvm() in > init_proc_POWER10 to initialize the registers with a random value. > I'm not sure what is the behavior here, I would expect that is the job > of the OS to set the regs, but looks like KVM is not exporting them, > so they are always 0 (?). Does anyone have any insight on this? This happens because KVM on POWER10 isn't handling these registers appropriately. We are probably missing kernel/kvm code to do so. Since KVM on POWER10 is on an uncertain spot at this moment I wouldn't worry too much about it. Making the regs read/write work in TCG is good enough for now. Daniel > > v1->v2: > - Split the patch in 2 > - Rebase to master > > v2->v3: > - Split patches in 3 > - the new patch (patch 1) is separating the kvm header > changes [Cornelia] > > [1] https://eprint.iacr.org/2013/404.pdf > > Víctor Colombo (3): > linux-headers/asm-powerpc/kvm.h: Add HASHKEYR and HASHPKEYR in headers > target/ppc: Implement hashst and hashchk > target/ppc: Implement hashstp and hashchkp > > linux-headers/asm-powerpc/kvm.h | 3 + > target/ppc/cpu.h | 2 + > target/ppc/cpu_init.c | 7 ++ > target/ppc/excp_helper.c | 82 ++++++++++++++++++++++ > target/ppc/helper.h | 4 ++ > target/ppc/insn32.decode | 10 +++ > target/ppc/translate.c | 5 ++ > target/ppc/translate/fixedpoint-impl.c.inc | 34 +++++++++ > 8 files changed, 147 insertions(+) >
On 15/07/2022 10:23, Daniel Henrique Barboza wrote: > On 7/13/22 13:54, Víctor Colombo wrote: >> This patch series implements the 4 instructions added in Power ISA >> 3.1B: >> >> - hashchk >> - hashst >> - hashchkp >> - hashstp >> >> To build it, you need to apply the following patches on top of master: >> <20220701133507.740619-2-lucas.coutinho@eldorado.org.br> >> <20220701133507.740619-3-lucas.coutinho@eldorado.org.br> >> <20220712193741.59134-2-leandro.lupori@eldorado.org.br> >> <20220712193741.59134-3-leandro.lupori@eldorado.org.br> >> >> Working branch for ease of use can be found here: >> https://github.com/PPC64/qemu/tree/vccolombo-hash-to-send-v3 >> >> What do you think about the choice to implement the hash algorithm >> from the ground up, following the SIMON-like algorithm presented in >> Power ISA? IIUC, this algorithm is not the same as the original[1]. >> Other options would be to use other algorithm already implemented >> in QEMU, or even make this instruction a nop for all Power versions. >> >> Also, I was thinking about using the call to spr_register_kvm() in >> init_proc_POWER10 to initialize the registers with a random value. >> I'm not sure what is the behavior here, I would expect that is the job >> of the OS to set the regs, but looks like KVM is not exporting them, >> so they are always 0 (?). Does anyone have any insight on this? > > This happens because KVM on POWER10 isn't handling these registers > appropriately. We are probably missing kernel/kvm code to do so. > > Since KVM on POWER10 is on an uncertain spot at this moment I wouldn't > worry too much about it. Making the regs read/write work in TCG is good > enough for now. > > > Daniel Hello Daniel, Thanks for taking a look at this. I agree that in this case it is better to make it work in TCG and drop the KVM part from this patch set I'll work on it now Thanks! > >> >> v1->v2: >> - Split the patch in 2 >> - Rebase to master >> >> v2->v3: >> - Split patches in 3 >> - the new patch (patch 1) is separating the kvm header >> changes [Cornelia] >> >> [1] https://eprint.iacr.org/2013/404.pdf >> >> Víctor Colombo (3): >> linux-headers/asm-powerpc/kvm.h: Add HASHKEYR and HASHPKEYR in headers >> target/ppc: Implement hashst and hashchk >> target/ppc: Implement hashstp and hashchkp >> >> linux-headers/asm-powerpc/kvm.h | 3 + >> target/ppc/cpu.h | 2 + >> target/ppc/cpu_init.c | 7 ++ >> target/ppc/excp_helper.c | 82 ++++++++++++++++++++++ >> target/ppc/helper.h | 4 ++ >> target/ppc/insn32.decode | 10 +++ >> target/ppc/translate.c | 5 ++ >> target/ppc/translate/fixedpoint-impl.c.inc | 34 +++++++++ >> 8 files changed, 147 insertions(+) >>
This patch series implements the 4 instructions added in Power ISA 3.1B: - hashchk - hashst - hashchkp - hashstp To build it, you need to apply the following patches on top of master: <20220701133507.740619-2-lucas.coutinho@eldorado.org.br> <20220701133507.740619-3-lucas.coutinho@eldorado.org.br> <20220712193741.59134-2-leandro.lupori@eldorado.org.br> <20220712193741.59134-3-leandro.lupori@eldorado.org.br> Working branch for ease of use can be found here: https://github.com/PPC64/qemu/tree/vccolombo-hash-to-send-v3 What do you think about the choice to implement the hash algorithm from the ground up, following the SIMON-like algorithm presented in Power ISA? IIUC, this algorithm is not the same as the original[1]. Other options would be to use other algorithm already implemented in QEMU, or even make this instruction a nop for all Power versions. Also, I was thinking about using the call to spr_register_kvm() in init_proc_POWER10 to initialize the registers with a random value. I'm not sure what is the behavior here, I would expect that is the job of the OS to set the regs, but looks like KVM is not exporting them, so they are always 0 (?). Does anyone have any insight on this? v1->v2: - Split the patch in 2 - Rebase to master v2->v3: - Split patches in 3 - the new patch (patch 1) is separating the kvm header changes [Cornelia] [1] https://eprint.iacr.org/2013/404.pdf Víctor Colombo (3): linux-headers/asm-powerpc/kvm.h: Add HASHKEYR and HASHPKEYR in headers target/ppc: Implement hashst and hashchk target/ppc: Implement hashstp and hashchkp linux-headers/asm-powerpc/kvm.h | 3 + target/ppc/cpu.h | 2 + target/ppc/cpu_init.c | 7 ++ target/ppc/excp_helper.c | 82 ++++++++++++++++++++++ target/ppc/helper.h | 4 ++ target/ppc/insn32.decode | 10 +++ target/ppc/translate.c | 5 ++ target/ppc/translate/fixedpoint-impl.c.inc | 34 +++++++++ 8 files changed, 147 insertions(+)