[00/19] Multiple ppc instructions fixes

Message

Víctor Colombo Sept. 1, 2022, 1:17 p.m. UTC

This patch set fixes multiple instructions for PPC targets that were
producing incorrect results, or setting the wrong bits in FPSCR.

Patch 1 is just a style fix, trivial.
Patches 8 through 19 add helper_reset_fpstatus() calls to instructions
    that have an issue where the exception flags are being kept from
    the previous instruction, causing incorrect bits to be set,
    specially the non-sticky FI bit.
Other patches fixes other specific situations.

Víctor Colombo (19):
  target/ppc: Remove extra space from s128 field in ppc_vsr_t
  target/ppc: Remove unused xer_* macros
  target/ppc: Zero second doubleword in DFP instructions
  target/ppc: Set result to QNaN for DENBCD when VXCVI occurs
  target/ppc: Zero second doubleword for VSX madd instructions
  target/ppc: Set OV32 when OV is set
  target/ppc: Zero second doubleword of VSR registers for FPR insns
  target/ppc: Clear fpstatus flags on VSX_CVT_INT_TO_FP_VECTOR
  target/ppc: Clear fpstatus flags on VSX_CVT_INT_TO_FP
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT_VECTOR
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT2
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_INT
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_HP
  target/ppc: Clear fpstatus flags on VSX_CVT_FP_TO_FP_VECTOR
  target/ppc: Clear fpstatus flags for xscvqpdp
  target/ppc: Clear fpstatus flags for xscvdpsp[n]
  target/ppc: Clear fpstatus flags on VSX_CMP
  target/ppc: Clear fpstatus flags on VSX_ROUND

 target/ppc/cpu.h        |  6 +-----
 target/ppc/dfp_helper.c | 31 ++++++++++++++++++++++++++++---
 target/ppc/fpu_helper.c | 39 +++++++++++++++++++++++++++------------
 target/ppc/int_helper.c |  4 ++--
 target/ppc/translate.c  |  8 ++++++++
 5 files changed, 66 insertions(+), 22 deletions(-)