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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id 196-20020a6306cd000000b0042a4612c07esm513172pgg.39.2022.09.09.06.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 06:42:19 -0700 (PDT) From: Bin Meng To: qemu-devel@nongnu.org Cc: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support Date: Fri, 9 Sep 2022 21:42:07 +0800 Message-Id: <20220909134215.1843865-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset refactors RISC-V Debug support to allow more types of triggers to be extended. The initial support of type 6 trigger, which is similar to type 2 trigger with additional functionality, is also introduced in this patchset. This is a v2 respin of previous patch originally done by Frank Chang at SiFive. I've incorperated my review comments in v2 and rebased against QEMU mainline. Changes in v2: - fixed MXL_RV128 case - moved macros to patch#2 - added log guest errors for TRIGGER_TYPE_{NO_EXIST,UNAVAIL} - moved RV{32,64}_DATA_MASK definition to this patch - add handling of the DBG_ACTION_NONE case in do_trigger_action() - drop patch: "target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers" Frank Chang (8): target/riscv: debug: Determine the trigger type from tdata1.type target/riscv: debug: Introduce build_tdata1() to build tdata1 register content target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs target/riscv: debug: Restrict the range of tselect value can be written target/riscv: debug: Introduce tinfo CSR target/riscv: debug: Create common trigger actions function target/riscv: debug: Check VU/VS modes for type 2 trigger target/riscv: debug: Add initial support of type 6 trigger target/riscv/cpu.h | 6 +- target/riscv/cpu_bits.h | 1 + target/riscv/debug.h | 55 +++-- target/riscv/csr.c | 10 +- target/riscv/debug.c | 484 ++++++++++++++++++++++++++++++++-------- target/riscv/machine.c | 20 +- 6 files changed, 445 insertions(+), 131 deletions(-)