From patchwork Fri Nov 18 12:37:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13048212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0960C4321E for ; Fri, 18 Nov 2022 12:40:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ow0eP-0005wV-6I; Fri, 18 Nov 2022 07:39:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ow0dx-0005p8-LT; Fri, 18 Nov 2022 07:38:54 -0500 Received: from smtp84.cstnet.cn ([159.226.251.84] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ow0dr-0007ey-Uw; Fri, 18 Nov 2022 07:38:51 -0500 Received: from localhost.localdomain (unknown [180.165.240.202]) by APP-05 (Coremail) with SMTP id zQCowACHj7fNfHdjlWwsCg--.62094S2; Fri, 18 Nov 2022 20:38:39 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v5 0/9] support subsets of code size reduction extension Date: Fri, 18 Nov 2022 20:37:19 +0800 Message-Id: <20221118123728.49319-1-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowACHj7fNfHdjlWwsCg--.62094S2 X-Coremail-Antispam: 1UD129KBjvJXoW7uryDKr18Wr4UGF4rAF48Crg_yoW8KFyrpr WrC3yakrZ8tFWxJw4ftF1DJw15Ar4rWr45Awn7Jw1kJay3ArW5Jrn7K3W3G3WxJF18WrnF 93WUCw13u3yUJFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyG14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vI r41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8Gjc xK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0 cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8V AvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E 14v26r4UJVWxJrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-Originating-IP: [180.165.240.202] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.84; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v5 To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extension support. This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test v5: * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt v4: * improve Zcmp suggested by Richard * fix stateen related check for Zcmt v3: * update the solution for Zcf to the way of Zcd * update Zcb to reuse gen_load/store * use trans function instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension target/riscv: add support for Zcmp extension target/riscv: add support for Zcmt extension target/riscv: expose properties for Zc* extension disas/riscv.c: add disasm support for Zc* disas/riscv.c | 287 +++++++++++++++++++- target/riscv/cpu.c | 56 ++++ target/riscv/cpu.h | 10 + target/riscv/cpu_bits.h | 7 + target/riscv/csr.c | 38 ++- target/riscv/helper.h | 3 + target/riscv/insn16.decode | 63 ++++- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ target/riscv/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ target/riscv/machine.c | 19 ++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 15 +- target/riscv/zce_helper.c | 55 ++++ 15 files changed, 893 insertions(+), 16 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc create mode 100644 target/riscv/zce_helper.c