From patchwork Fri Dec 23 08:50:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 13080759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E759C3DA7A for ; Fri, 23 Dec 2022 08:51:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p8dli-0007MG-Ea; Fri, 23 Dec 2022 03:51:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p8dlb-0007K1-MM; Fri, 23 Dec 2022 03:51:00 -0500 Received: from mail.csgraf.de ([85.25.223.15] helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p8dlZ-00046s-NN; Fri, 23 Dec 2022 03:50:59 -0500 Received: from localhost.localdomain (dynamic-095-118-065-151.95.118.pool.telefonica.de [95.118.65.151]) by csgraf.de (Postfix) with ESMTPSA id 84912608042C; Fri, 23 Dec 2022 09:50:48 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Yanan Wang , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum , Eduardo Habkost , Shashi Mallela , Eric Auger , Neil Armstrong Subject: [PATCH 0/2] hw/intc/arm_gicv3: Bump ITT entry size to 16 Date: Fri, 23 Dec 2022 09:50:45 +0100 Message-Id: <20221223085047.94832-1-agraf@csgraf.de> X-Mailer: git-send-email 2.37.1 (Apple Git-137.1) MIME-Version: 1.0 Received-SPF: pass client-ip=85.25.223.15; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org While trying to make Windows work with GICv3 emulation, I stumbled over the fact that it only supports ITT entry sizes that are power of 2 sized. While the spec allows arbitrary sizes, in practice hardware will always expose power of 2 sizes and so this limitation is not really a problem in real world scenarios. However, we only expose a 12 byte ITT entry size which makes Windows blue screen on boot. The easy way to get around that problem is to bump the size to 16. That is a power of 2, basically is what hardware would expose given the amount of bits we need per entry and doesn't break any existing scenarios. To play it safe, this patch set only bumps them on newer machine types. Alexander Graf (2): hw/intc/arm_gicv3: Make ITT entry size configurable hw/intc/arm_gicv3: Bump ITT entry size to 16 hw/core/machine.c | 4 +++- hw/intc/arm_gicv3_its.c | 13 ++++++++++--- hw/intc/gicv3_internal.h | 2 +- include/hw/intc/arm_gicv3_its_common.h | 1 + 4 files changed, 15 insertions(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé