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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id e17-20020adfe7d1000000b0024cb961b6aesm4313537wrn.104.2023.01.23.01.03.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:03:26 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 0/5] riscv: Allow user to set the satp mode Date: Mon, 23 Jan 2023 10:03:19 +0100 Message-Id: <20230123090324.732681-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This introduces new properties to allow the user to set the satp mode, see patch 3 for full syntax. In addition, it prevents cpus to boot in a satp mode they do not support (see patch 5). v6: - Remove the valid_vm check in validate_vm and add it to the finalize function so that map already contains the constraint, Alex - Add forgotten mbare to satp_mode_from_str, Alex - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew - Only add satp mode properties corresponding to the cpu, and then remove the check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize, Andrew/Alistair/Alex - Move mmu-type setting to its own patch, Andrew - patch 5 is new and is a fix, Alex v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Correctly set the device-tree entry 'mmu-type' riscv: Introduce satp mode hw capabilities hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 247 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 23 +++++ target/riscv/csr.c | 29 +++--- 4 files changed, 287 insertions(+), 31 deletions(-)