[v2,0/5] Various xive fixes

Message

Frederic Barrat June 1, 2023, 12:13 p.m. UTC

A set of small fixes for the interrupt controller (xive2) on P10.

Change log:
v2:
  split last patch to do a bit of cleanup first
  add Cedric's reviewed-by on the first 3 patches

Frederic Barrat (5):
  pnv/xive2: Add definition for TCTXT Config register
  pnv/xive2: Add definition for the ESB cache configuration register
  pnv/xive2: Allow writes to the Physical Thread Enable registers
  pnv/xive2: Introduce macros to manipulate TIMA addresses
  pnv/xive2: Handle TIMA access through all ports

 hw/intc/pnv_xive2.c        | 20 +++++++++++++++++++-
 hw/intc/pnv_xive2_regs.h   |  8 ++++++++
 hw/intc/xive.c             | 16 ++++++++--------
 include/hw/ppc/xive_regs.h | 16 ++++++++++++++++
 4 files changed, 51 insertions(+), 9 deletions(-)

Comments

Daniel Henrique Barboza June 1, 2023, 8:30 p.m. UTC | #1

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

On 6/1/23 09:13, Frederic Barrat wrote:
> A set of small fixes for the interrupt controller (xive2) on P10.
> 
> Change log:
> v2:
>    split last patch to do a bit of cleanup first
>    add Cedric's reviewed-by on the first 3 patches
> 
> Frederic Barrat (5):
>    pnv/xive2: Add definition for TCTXT Config register
>    pnv/xive2: Add definition for the ESB cache configuration register
>    pnv/xive2: Allow writes to the Physical Thread Enable registers
>    pnv/xive2: Introduce macros to manipulate TIMA addresses
>    pnv/xive2: Handle TIMA access through all ports
> 
>   hw/intc/pnv_xive2.c        | 20 +++++++++++++++++++-
>   hw/intc/pnv_xive2_regs.h   |  8 ++++++++
>   hw/intc/xive.c             | 16 ++++++++--------
>   include/hw/ppc/xive_regs.h | 16 ++++++++++++++++
>   4 files changed, 51 insertions(+), 9 deletions(-)
>