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Thu, 1 Jun 2023 12:13:31 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 747292004B; Thu, 1 Jun 2023 12:13:31 +0000 (GMT) Received: from borneo.tlslab.ibm.com (unknown [9.101.4.34]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 1 Jun 2023 12:13:31 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 0/5] Various xive fixes Date: Thu, 1 Jun 2023 14:13:26 +0200 Message-Id: <20230601121331.487207-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: gN40YlRUjlK5oM6fOmz-X1296I-ID9EH X-Proofpoint-ORIG-GUID: Cvy9Ufmtgs4Q3u2au4Ybbdy8wLx6C8Oi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=518 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010107 Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A set of small fixes for the interrupt controller (xive2) on P10. Change log: v2: split last patch to do a bit of cleanup first add Cedric's reviewed-by on the first 3 patches Frederic Barrat (5): pnv/xive2: Add definition for TCTXT Config register pnv/xive2: Add definition for the ESB cache configuration register pnv/xive2: Allow writes to the Physical Thread Enable registers pnv/xive2: Introduce macros to manipulate TIMA addresses pnv/xive2: Handle TIMA access through all ports hw/intc/pnv_xive2.c | 20 +++++++++++++++++++- hw/intc/pnv_xive2_regs.h | 8 ++++++++ hw/intc/xive.c | 16 ++++++++-------- include/hw/ppc/xive_regs.h | 16 ++++++++++++++++ 4 files changed, 51 insertions(+), 9 deletions(-)