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[v2,0/3] target/riscv: Fix mstatus related problems

Message ID 20230603134236.15719-1-liweiwei@iscas.ac.cn (mailing list archive)
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Series target/riscv: Fix mstatus related problems | expand

Message

Weiwei Li June 3, 2023, 1:42 p.m. UTC
This patchset tries to fix some problems in the fields of mstatus, such as make MPV only work when MPP != PRM.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream-v2

v2:
* Drop patch 3 (remove check on mode M for MPRV)
* rebase on apply-to-riscv.next

Weiwei Li (3):
  target/riscv: Make MPV only work when MPP != PRV_M
  target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
  target/riscv: Remove redundant assignment to SXL

 target/riscv/cpu_helper.c |  3 ++-
 target/riscv/csr.c        | 14 ++++----------
 target/riscv/op_helper.c  |  3 ++-
 3 files changed, 8 insertions(+), 12 deletions(-)

Comments

Alistair Francis June 22, 2023, 1:52 a.m. UTC | #1
On Sat, Jun 3, 2023 at 11:43 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset tries to fix some problems in the fields of mstatus, such as make MPV only work when MPP != PRM.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-mpv-upstream-v2
>
> v2:
> * Drop patch 3 (remove check on mode M for MPRV)
> * rebase on apply-to-riscv.next
>
> Weiwei Li (3):
>   target/riscv: Make MPV only work when MPP != PRV_M
>   target/riscv: Support MSTATUS.MPV/GVA only when RVH is enabled
>   target/riscv: Remove redundant assignment to SXL

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu_helper.c |  3 ++-
>  target/riscv/csr.c        | 14 ++++----------
>  target/riscv/op_helper.c  |  3 ++-
>  3 files changed, 8 insertions(+), 12 deletions(-)
>
> --
> 2.25.1
>
>