[v3,0/8] TriCore 1.6.2 Instructions

Message

Bastian Koppelmann June 14, 2023, 10 a.m. UTC

Hi,

this patch series is in response to the tickets [1] [2], which point out missing
instructions from ISA v1.6.2. This is the first series that implements the low
hanging fruits.

Cheers,
Bastian

v1 -> v2:
    - Shuffle now uses shifts, instead of a buffer
    - Shuffle now does rev8 for all bytes in parallel

v2 -> v3:
    - Added patch to implement SYSCALL (resolves https://gitlab.com/qemu-project/qemu/-/issues/1452)
    - Added patch to implement DISABLE insn variant

Bastian Koppelmann (8):
  target/tricore: Introduce ISA 1.6.2 feature
  target/tricore: Add popcnt.w insn
  target/tricore: Add LHA insn
  target/tricore: Add crc32l.w insn
  target/tricore: Add crc32.b insn
  target/tricore: Add shuffle insn
  target/tricore: Implement SYCSCALL insn
  target/tricore: Add DISABLE insn variant

 target/tricore/cpu.c             | 13 +++++++
 target/tricore/cpu.h             |  1 +
 target/tricore/helper.h          |  5 ++-
 target/tricore/op_helper.c       | 54 +++++++++++++++++++++++++++-
 target/tricore/translate.c       | 61 ++++++++++++++++++++++++++++----
 target/tricore/tricore-opcodes.h | 16 +++++++--
 6 files changed, 140 insertions(+), 10 deletions(-)