mbox series

[v2,0/8] TriCore Privilege Levels

Message ID 20230616152808.1499082-1-kbastian@mail.uni-paderborn.de (mailing list archive)
Headers show
Series TriCore Privilege Levels | expand

Message

Bastian Koppelmann June 16, 2023, 3:28 p.m. UTC 
Hi,

this patch series tries to properly implement privilege levels for the TriCore,
as discussed in
https://lore.kernel.org/qemu-devel/20230118090319.32n4uto7ogy3gfr6@schnipp.zuhause/.

While implementing privilege traps for the SV/UM1 only insns, I saw that
the RESTORE insn uses the wrong ICR.IE bit. So I fixed that as well.

Cheers,
Bastian

v1 -> v2:
    - Fixed bug where JLI clobbered reg A[11]          | PATCH [01/08]
    - Moved all calls to tcg_gen_exit_tb() to          | PATCH [02/08]
      tricore_tr_tb_stop()                             |
    - Enable/disable insns now exit to main-loop       | PATCH [03/08]
    - Indirect jumps us tcg_gen_lookup_and_goto_ptr()  | PATCH [04/08]
    - Removed (uint32_t) cast                          | PATCH [05/08]
    - Removed psw_write() calling cpu_loop_exit()      | PATCH [07/08]

Bastian Koppelmann (8):
  target/tricore: Fix RR_JLI clobbering reg A[11]
  target/tricore: Introduce DISAS_TARGET_EXIT
  target/tricore: ENABLE/DISABLE exit to main-loop
  target/tricore: Indirect jump insns use tcg_gen_lookup_and_goto_ptr()
  target/tricore: Introduce priv tb flag
  target/tricore: Implement privilege level for all insns
  target/tricore: Honour privilege changes on PSW write
  target/tricore: Fix ICR.IE offset in RESTORE insn

 target/tricore/cpu.h       | 17 +++++--
 target/tricore/translate.c | 98 ++++++++++++++++++++++++++------------
 2 files changed, 79 insertions(+), 36 deletions(-)

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2.40.1