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([152.234.123.64]) by smtp.gmail.com with ESMTPSA id ks19-20020a056a004b9300b006d977f70cd5sm8125940pfb.23.2024.01.15.14.25.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jan 2024 14:25:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, max.chou@sifive.com, Daniel Henrique Barboza Subject: [PATCH v2 00/12] target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' Date: Mon, 15 Jan 2024 19:25:16 -0300 Message-ID: <20240115222528.257342-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This v2 contains changes proposed after the review from Richard. Most notable change is in patch 11, where we simplified our lives a bit and just calculated 'vlmax' using 'vlenb' instead of trying to use the TCG global 'cpu_vl'. Patch 10 also changed a bit to avoid the negative shift we were doing in v1. Changes from v1: - patch 8: - instead of shifting sew, adjust the amount of shift rights to use 'vlenb' - patch 9: - adjust the shifts rights to use 'vlenb' instead of shifting 'vlenb' left beforehand - patch 10: - calc 'max_sz' before doing shift rights to retrieve MAX_SZ() - patches 11 and 12: - squashed together - calc 'vlmax' using the same logic from patch 9 in both functions - v1 link: https://lore.kernel.org/qemu-riscv/20240112213812.173521-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (12): target/riscv: add 'vlenb' field in cpu->cfg target/riscv/csr.c: use 'vlenb' instead of 'vlen' target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen' target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb' target/riscv/vector_helper.c: use 'vlenb' target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl) target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax() target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() trans_rvv.c.inc: use 'vlenb' to calc vlmax in trans_vrgather_v*() target/riscv/cpu.c: remove cpu->cfg.vlen target/riscv/cpu.c | 12 +- target/riscv/cpu.h | 6 +- target/riscv/cpu_cfg.h | 2 +- target/riscv/csr.c | 4 +- target/riscv/gdbstub.c | 6 +- target/riscv/insn_trans/trans_rvbf16.c.inc | 12 +- target/riscv/insn_trans/trans_rvv.c.inc | 152 ++++++++++----------- target/riscv/insn_trans/trans_rvvk.c.inc | 16 +-- target/riscv/tcg/tcg-cpu.c | 4 +- target/riscv/vector_helper.c | 26 ++-- 10 files changed, 124 insertions(+), 116 deletions(-)