From patchwork Tue Jan 23 12:22:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?In=C3=A8s_Varhol?= X-Patchwork-Id: 13527321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10BD7C47258 for ; Tue, 23 Jan 2024 12:27:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSFqr-0000i1-H2; Tue, 23 Jan 2024 07:26:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSFqG-0000Wu-Nn; Tue, 23 Jan 2024 07:25:24 -0500 Received: from zproxy3.enst.fr ([2001:660:330f:2::de]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSFqD-0002Fs-1c; Tue, 23 Jan 2024 07:25:24 -0500 Received: from localhost (localhost [IPv6:::1]) by zproxy3.enst.fr (Postfix) with ESMTP id 1FEF9A05C4; Tue, 23 Jan 2024 13:25:14 +0100 (CET) Received: from zproxy3.enst.fr ([IPv6:::1]) by localhost (zproxy3.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id etrq1au-SX-9; Tue, 23 Jan 2024 13:25:13 +0100 (CET) Received: from localhost (localhost [IPv6:::1]) by zproxy3.enst.fr (Postfix) with ESMTP id 2A041A065A; Tue, 23 Jan 2024 13:25:13 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy3.enst.fr 2A041A065A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1706012713; bh=tqPDx3vKPo8imUs2ABP3ymYy7Fs2Y0cI0+VAG/zvE70=; h=From:To:Date:Message-ID:MIME-Version; b=2HxZOZVsTkVP8Wpuewc0h4TLTe3YsqPWxAtB6zlA9th5iV5RWWWk312ptMOHIk2eF IjEnCuS0/6tsQMLNu6VOLFlZgYzFU8Xg4kRJlYJzzJpYGGTcyO3b5zr0+A/GoJ5ub+ ozrE+lkXNhgvnZk/bPuj28cjlR3CTIajbJoBAd3c= X-Virus-Scanned: amavis at enst.fr Received: from zproxy3.enst.fr ([IPv6:::1]) by localhost (zproxy3.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id uRncy-tr7_r2; Tue, 23 Jan 2024 13:25:13 +0100 (CET) Received: from localhost.localdomain (74.0.125.80.rev.sfr.net [80.125.0.74]) by zproxy3.enst.fr (Postfix) with ESMTPSA id A6C1CA014F; Tue, 23 Jan 2024 13:25:12 +0100 (CET) From: =?utf-8?q?In=C3=A8s_Varhol?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?In=C3=A8s_Varhol?= , Samuel Tardieu , Peter Maydell , Alistair Francis , qemu-arm@nongnu.org, Arnaud Minier , Laurent Vivier , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v3 0/3] Add device STM32L4x5 GPIO Date: Tue, 23 Jan 2024 13:22:51 +0100 Message-ID: <20240123122505.516393-1-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2001:660:330f:2::de; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy3.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds a new device STM32L4x5 GPIO device and is part of a series implementing the STM32L4x5 with a few peripherals. Changes from v2 : - correct memory leaks caused by re-assigning a `g_autofree` pointer without freeing it - gpio-test : test that reset values (and not just initialization values) are correct, correct `stm32l4x5_gpio_reset()` accordingly - adding a `clock-freq-hz` object property to test that enabling GPIO clock in RCC sets the GPIO clocks Changes from v1 : - replacing test GPIO register `DISCONNECTED_PINS` with an object property accessed using `qtest_qmp()` in the qtest (through helpers `get_disconnected_pins()` and `disconnect_all_pins()`) - removing GPIO subclasses and storing MODER, OSPEEDR and PUPDR reset values in properties - adding a `name` property and using it for more lisible traces - using `g_strdup_printf()` to facilitate setting irqs in the qtest, and initializing GPIO children in soc_initfn Changes from RFC v1 : - `stm32l4x5-gpio-test.c` : correct typos, make the test generic, add a test for bitwise writing in register ODR - `stm32l4x5_soc.c` : connect gpios to their clock, use an array of GpioState - `stm32l4x5_gpio.c` : correct comments in `update_gpio_idr()`, correct `get_gpio_pins_to_disconnect()`, correct `stm32l4x5_gpio_init()` and initialize the clock, add a realize function - update MAINAINERS Based-on: 20240118091107.87831-1-arnaud.minier@telecom-paris.fr ([PATCH v2 0/7] Add device STM32L4x5 RCC) Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol Inès Varhol (3): hw/gpio: Implement STM32L4x5 GPIO hw/arm: Connect STM32L4x5 GPIO to STM32L4x5 SoC tests/qtest: Add STM32L4x5 GPIO QTest testcase MAINTAINERS | 1 + docs/system/arm/b-l475e-iot01a.rst | 2 +- hw/arm/Kconfig | 3 +- hw/arm/stm32l4x5_soc.c | 78 +++- hw/gpio/Kconfig | 3 + hw/gpio/meson.build | 1 + hw/gpio/stm32l4x5_gpio.c | 456 ++++++++++++++++++++++ hw/gpio/trace-events | 6 + include/hw/arm/stm32l4x5_soc.h | 2 + include/hw/gpio/stm32l4x5_gpio.h | 70 ++++ tests/qtest/meson.build | 3 +- tests/qtest/stm32l4x5_gpio-test.c | 586 +++++++++++++++++++++++++++++ 12 files changed, 1194 insertions(+), 17 deletions(-) create mode 100644 hw/gpio/stm32l4x5_gpio.c create mode 100644 include/hw/gpio/stm32l4x5_gpio.h create mode 100644 tests/qtest/stm32l4x5_gpio-test.c